IS31FL3196A
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D, 04/27/2018
6
DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 5)
Symbol Parameter Condition
Standard Mode Fast Mode
Unit
Min. Typ. Max. Min. Typ. Max.
f
SCL
Serial-Clock frequency 100 400 kHz
t
BUF
Bus free time between a STOP and
a START condition
4.7 1.3 s
t
HD, STA
Hold time (repeated) START
condition
4.0 0.6 s
t
SU, STA
Repeated START condition setup
time
4.7 0.6 s
t
SU, STO
STOP condition setup time 4.0 0.6 s
t
HD, DAT
Data hold time (Note 6) 0 3.45 0 0.9 s
t
SU, DAT
Data setup time (Note 7) 250 100 ns
t
LOW
SCL clock low period 4.7 1.3 s
t
HIGH
SCL clock high period 4.0 0.7 s
t
R
Rise time of both SDA and SCL
signals, receiving (Note 8)
1000 20+0.1C
b
300 ns
t
F
Fall time of both SDA and SCL
signals, receiving (Note 8)
300 20+0.1C
b
300 ns
Note 3: The average current of each channel is I
OUT
.
Note 4: All LEDs are on.
Note 5: Guaranteed by design.
Note 6: The minimum t
HD, DAT
measured start from V
IL
(max) of SCL signal. The maximum t
HD,DAT
has only to be met if the device does not stretch
the LOW period (t
LOW
) of the SCL signal. V
IL
(max)
Note 7: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t
SU,DAT
250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t
R
max + t
SU,DAT
= 1000 + 250 = 1250ns (according to the Standard-mode I2C-bus
specification) before the SCL line is released.
Note 8: C
b
= total capacitance of one bus line in pF. I
SINK
6mA. t
R
and t
F
measured between 0.3 × V
CC
and 0.7 × V
CC
.
