MAX9225/MAX9226
Applications Information
PCLKIN Latch Edge
The parallel data input of the MAX9225 serializer is
latched on the rising edge of PCLKIN. Figure 3 shows
the serializer input timing.
PCLKOUT Strobe
The serial-data output of the MAX9226 deserializer is
valid on the rising edge of PCLKOUT. Figure 4 shows
the deserializer output timing.
Power-Down and Power-Up
Driving PWRDN low puts the MAX9225 in power-down
mode and sends a pulse to power down the MAX9226.
In power-down mode, the DLL is stopped, SDO+/SDO-
are high impedance to ground and differential, and the
LCDS link is weakly biased around (V
DD
- 0.8V). With
PWRDN and all inputs low, the combined MAX9225/
MAX9226 supply current is reduced to 3.5µA or less.
Driving PWRDN high starts DLL lock to PCLKIN and ini-
tiates a MAX9226 power-up sequence. The MAX9225
LCDS output is not driven until the DLL locks. 11,264
clock cycles are required for the power-up and link syn-
chronization before valid DIN can be latched. See
Figure 6 for an overall power-up and power-down tim-
ing diagram. For normal operation, PCLKIN must be
running and settled before driving PWRDN high.
If V
DD
= 0, the LCDS outputs are high impedance to
ground and differential.
Ground-Shift Tolerance
The MAX9225/MAX9226 are designed to function nor-
mally in the event of a slight shift in ground potential.
However, the MAX9226 deserializer ground must be
within ±0.2V relative to the MAX9225 serializer ground
to maintain proper operation.
MAX9226 Output Buffer Supply (V
DDO
)
The MAX9226 parallel outputs are powered from V
DDO
,
which accepts a +1.71V to +3.465V supply, allowing
direct interface to inputs with 1.8V to 3.3V logic levels.
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
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