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KSZ8721BLI-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
Micrel, Inc. KS8721BL/SL
June 2009
16
M9999-062509-1.3
10/100 BASE-T
Media Dependent Interface
10/10
0
BASE-T
Media Dependent Interface
Transmit Pair
Receive Pair
Transmit Pair
Receive Pair
Modular Connector (RJ45)
HUB
(Repeater or Switch)
Modular Connector (RJ45)
HUB
(Repeater or Switch)
Figure 2. Crossover Cable
Power Management
The KS8721BL/SL offers the following modes for power management:
• Power-Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# low.
• Power-Saving Mode: This mode can be disabled by writing to Register 1fh.10. The KS8721BL/SL turns off
everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the
KS8721BL/SL shuts down most of the internal circuits to save power if there is no link. Power-saving mode is in
the most effective state when auto-negotiation mode is enabled.
100BT FX Mode
Please contact your local field application engineer (FAE) for a reference schematic on fiber connection.
100BT FX mode is activated when FXSD/FXEN is higher than 0.6V (this pin has a default pull down). Under this mode,
the auto-negotiation and auto-MDI-X features are disabled.
In fiber operation, the FXSD pin should connect to the signal detect (SD) output of the fiber module. The internal
threshold of FXSD is around 1/2 V
DD
±50mV (1.25V ±0.05V). Above this level, the fiber signal is considered detected.
The operation is summarized in the following table:
FXSD/FXEN Condition
Less than 0.6V 100TX mode
Less than 1.25V,
but greater than 0.6V
FX mode
No signal detected
FEF generated
Greater than 1.25
FX mode
Signal detected
Table 1. 100BT FX Mode
To ensure proper operation, the swing of fiber module SD should cover the threshold variation. A resistive voltage
divider is recommended to adjust the SD voltage range.
Far End Fault (FEF), repetition of a special pattern which consists of 84-one and 1-zero, is generated under “FX mode
with no signal detected.” The purpose of FEF is to notify the sender of a faulty link. When receiving an FEF, the LINK
will go down to indicate a fault, even with fiber signal detected. The transmitter is not affected by receiving an FEF and
Micrel, Inc. KS8721BL/SL
June 2009
17
M9999-062509-1.3
still sends out its normal transmit pattern from MAC. FEF can be disabled by strapping pin 27 low. Refer to the
“Strapping Options” section.
Media Converter Operation
The KS8721BL/SL is capable of performing media conversion with two parts in a back-to-back RMII loop-back mode as
indicated in the diagram. Both parts are in RMII mode and with RMII BTB asserted (pins 21 and 22 strapped high). One
part is operating in TX mode and the other is operating in FX mode. Both parts can share a common 50MHz oscillator.
Under this operation, auto-negotiation on the TX side prohibits 10BASE-T link-up. Additional options can be
implemented under this operation. Disable the transmitter and set it at tri-state by controlling the high TXD2 pin. In order
to do this, RXD2 and TXD2 pins need to be connected via inverter. When TXD2 pin is high in both the copper and fiber
operation, it is disabled transmit. Meanwhile, the RXD2 pin on the copper side serves as the energy detect and can
indicate if a line signal is detected. TXD3 should be tied low and RXD3 let float. Please contact your Micrel FAE for a
media converter reference design.
Rx
+/-
Tx +/-
FTx
FR
x
Pin
34
TxD
(Fiber Mode)
21 22
Pin
Pin
21 22
50MHz
V
CC
OSC
TxC/
Ref_CLK
TxC/
Ref_CLK
RxD
RxD
V
CC
KS8721BL/SL
KS8721BL/SL
To the SD pin of the
Fiber Module
TxD
Figure 3. Fiber Module
Micrel, Inc. KS8721BL/SL
June 2009
18
M9999-062509-1.3
Circuit Design Reference for Power Supply
Micrel’s integrated built-in, voltage regulator technology and thoughtful implementation allows the user to save BOM
cost on both existing and future designs with the use of the new KS8721BL/SL single supply, single port 10/100
Ethernet PHY.
7
24
+3.3V
KS8721BL/SL
8 12233536394344
VDDI/O
VDDI/O
VDDC VDDPLL
Voltage
Regulator
10F
+2.5V +2.5VPLL
Ferrite Bead
10F
10F 10F
13 47
+2.5VA
Ferrite Bead
VDDTX
OUTIN
GND
42 31 38
10F 10F
VDDRX
VDDRCV
Figure 4. Circuit Design
The circuit design in Figure 4 shows the power connections for the power supply: the 3.3V to VDDI/O is the only input
power source and the 2.5V at VDDRCV, pin 38, is the output of the voltage regulator that needs to supply through the
rest of the 2.5V VDD pins via the 2.5V power plane.
The 2.5V VDD pins make the drop-in replacement with the existing KS8721B/BT part. Table 2 shows the drop-in
replacement from the existing KS8721B/BT to the KS8721SL/BL. Please contact your local Micrel FAE for Application
Note AN-117, “Drop-in Replacement with KS8721BT.”
2.5V/3.3V Supply 3.3V Supply with Built-in Regulator
Part Number Package Part Number Package
KS8721B 48-SSOP KS8721SL 48-SSOP
KS8721BT 48-TQFP KS8721BL 48-LQFP
KS8721BI 48-SSOP KS8721SLI 48-SSOP
Table 2. Drop-In Replacement
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

KSZ8721BLI-TR

Mfr. #:
Buy KSZ8721BLI-TR
Manufacturer:
Microchip Technology / Micrel
Description:
Ethernet ICs 10/100 BASE-TX/FX Physical Layer Transceiver
Lifecycle:
New from this manufacturer.
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