HI5805EVAL1 Datasheet HI5805EVAL1 | P4-P6

3-4

Reference Generator, V

ROUT

and V

RIN

The HI5805 has an internal reference voltage generator,

therefore no external reference voltage is required. V

ROUT

must be connected to V

RIN

when using the internal

reference. Internal to the converter, two reference voltages

of 1.3V and 3.3V are generated making for a fully differential

analog input signal range of

±2V.

The HI5805 can be used with an external reference. The

converter requires only one external reference voltage

connected to the V

RIN

pin with V

ROUT

left open. The

evaluation board is configured with V

ROUT

connected to V

RIN

through a 0Ω resistor, R

. If it is desired to evaluate the

performance of the converter utilizing an externally provided

reference voltage, R

can be removed and the alternate

reference voltage can be brought in through twisted pair wire or

coaxial cable. The latter would be the recommended method

since it would provide the greatest immunity to externally

coupled noise voltages. In order to minimize overall converter

noise it is recommended that adequate high frequency

decoupling be provided at the reference input pin, V

RIN

Analog Input

The fully differential analog input of the HI5805 A/D can be

conﬁgured in various ways depending on the signal source

and the required level of performance.

Differential Analog Input Conﬁguration

A fully differential connection (Figure 3) will yield the best

performance from the HI5805 A/D converter. Since the

HI5805 is powered off a single +5V supply, the analog input

must be biased so it lies within the analog input common

mode voltage range of 1.0V to 4.0V. Figure 4 illustrates the

differential analog input common mode voltage range that

the converter will accommodate. The performance of the

ADC does not change signiﬁcantly with the value of the

common mode voltage.

A 2.3V DC bias voltage source, VDC, half way between the top

and bottom internally generated reference voltages, is made

available to the user to help simplify circuit design when using a

differential input. This low output impedance voltage source is

not designed to be a reference but makes an excellent bias

source and stays within the analog input common mode

voltage range over temperature. The DC voltage source has a

temperature coefficient of about +200ppm/

The difference between the converter's two internally

generated voltage references is 2V. For the AC coupled

differential input, (Figure 3), if V

is a 2V

P-P

sinewave with -

being 180 degrees out of phase with V

, the converter

will be at positive full scale when the V

IN+

input is at V

+1V

and the V

IN-

input is at V

- 1V (V

IN+

- V

IN-

= +2V).

Conversely, the ADC will be at negative full scale when the

IN+

input is equal to V

- 1V and V

IN-

is at V

+1V(V

IN+

- V

IN-

= -2V).

Evaluation Board Layout and Power Supplies

The HI5805 evaluation board is a four layer board with a layout

optimized for the best performance of the ADC. This application

note includes an electrical schematic of the evaluation board, a

component parts list, a component placement layout drawing

and reproductions of the various board layers used in the board

stack-up. The user should feel free to copy the layout in their

application. Refer to the component layout and the evaluation

board electrical schematic for the following discussions.

The HI5805 monolithic A/D converter has been designed

with separate analog and digital supply and ground pins to

keep digital noise out of the analog signal path. The

evaluation board provides separate low impedance analog

and digital ground planes on layer 2. Since the analog and

digital ground planes are connected together at a single

point where the power supplies enter the board, DO NOT tie

them together back at the power supplies.

The analog and digital supplies are also kept separate on

the evaluation board and should be driven by clean linear

regulated supplies. The external power supplies can be

hooked up with wires to the plated through holes marked

+5VAIN, +5VAIN1, -5VAIN, +5VDIN, +5VD1IN, +5VD2IN,

-5VDIN, AGND and DGND near the analog prototyping area.

+5VDIN, +5VD1IN, +5VD2IN and -5VDIN are digital

supplies and should be returned to DGND. +5VAIN,

+5VAIN1 and -5VAIN are the analog supplies and should be

returned to AGND. Table 1 lists the operational supply

voltages, typical current consumption and the evaluation

board circuit function being powered. Single supply

operation of the converter is possible but the overall

performance of the converter may degrade.

HI5805

-V

FIGURE 3. AC COUPLED DIFFERENTIAL INPUT

+ V

2.0V

P-P

VDC = 4.0V

+5V

2.0V

P-P

1.0V < VDC < 4.0V

2.0V

P-P

VDC = 1.0V

+5V

FIGURE 4. DIFFERENTIAL ANALOG INPUT COMMON MODE

VOLTAGE RANGE

Application Note 9707

3-5

It should be noted that overdriving the analog input beyond

the ±2.0V fullscale input voltage range will not damage the

converter as long as the overdrive voltage stays within the

converters analog supply voltages. In the event of an

overdrive condition the converter will recover within one

sample clock cycle.

Sample Clock Driver, Timing and I/O

In order to ensure rated performance of the HI5805, the duty

cycle of the sample clock should be held at 50% ±5%. It must

also have low phase noise and operate at standard TTL levels.

A voltage comparator (U3) with TTL output levels is provided on

the evaluation board to generate the sampling clock for the

HI5805 when a sinewave (< ±3V) or squarewave clock is

applied to the CLK input (J1) of the evaluation board. A

potentiometer (VR1) is provided to allow the user to adjust the

duty cycle of the sampling clock to obtain the best performance

from the ADC and to allow the user to investigate the effects of

expected duty cycle variations on the performance of the

converter. The HI5805 clock input trigger level is approximately

1.5V. Therefore, the duty cycle of the sampling clock should be

measured at this 1.5V trigger level. Test point TP4 provides a

convenient point to monitor the sample clock duty cycle and

make any required adjustments.

Figure 5 shows the sample clock and digital data timing

relationship for the evaluation board. The data

corresponding to a particular sample will be available at the

digital data outputs of the HI5805 after the data latency time,

LAT

, of 3 sample clock cycles plus the HI5805 digital data

output delay, t

. Table 2 lists the values that can be

expected for the indicated timing delays. Refer to the HI5805

data sheet for additional timing information.

The sample clock and digital output data signals are made

available through two connectors contained on the evaluation

board. The line buffering provided by the data output latches

allows for driving long leads or analyzer inputs. These data

latches are not necessary for the digital output data if the load

presented to the converter does not exceed the data sheet load

limits of one standard TTL load and 10pF. The P1 I/O connector

allows the evaluation board to be interfaced to the DSP

evaluation boards available from Intersil. Alternatively, the

digital output data and sample clock can also be accessed by

clipping the test leads of a logic analyzer or data acquisition

system onto the I/O pins of connector header P2.

TABLE 1. HI5805 EVALUATION BOARD POWER SUPPLIES

POWER

SUPPLY

NOMINAL

VALUE

CURRENT

(TYP)

FUNCTION(S)

SUPPLIED

+5VAIN 5.0V ±5% 22mA Op Amps

+5VAIN1 5.0V ±5% 46mA A/D AV

-5VAIN -5.0V ±5% 22mA Op Amps

+5VDIN 5.0V ±5%3 43mA CLK Comparator,

D0-D11 D-FF

+5VD1IN 5.0V ±5% 13mA A/D DV

CC1

and

CC2

+5VD2IN 5.0V ±5% 1mA A/D DV

CC3

-5VDIN -5.0V ±5% 3mA CLK Comparator

TABLE 2. TIMING SPECIFICATIONS

PARAMETER DESCRIPTION TYP

HI5805 Digital Output Data Delay 8ns

PD1

U3 Prop Delay 4.5ns

PD2

U5/6 Prop Delay 9ns

SINEWAVE CLK IN

HI5805 SAMPLE

CLOCK INPUT

HI5805 DIGITAL

DATA OUTPUT

CLOCK OUT

DIGITAL DATA OUTPUTS

PD2

(74ALS574)

PD1

DATA N

DATA NDATA N-1

(J1)

(CLK)

(D0 - D11)

(CLK AT TP4, P1-C20 OR P2-13)

DATA N-1

FIGURE 5. EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS

Application Note 9707

3-6

HI5805 Performance Characterization

Dynamic testing is used to evaluate the performance of the

HI5805 A/D converter. Among the tests performed are Signal-

to-Noise and Distortion Ratio (SINAD), Signal-to-Noise Ratio

(SNR), Total Harmonic Distortion (THD), Spurious Free

Dynamic Range (SFDR) and Intermodulation Distortion (IMD).

Figure 6 shows the test system used to perform dynamic

testing on high-speed ADCs at Intersil. The clock (CLK) and

analog input (V

) signals are sourced from low phase noise

HP8662A synthesized signal generators that are phase locked

to each other to ensure coherence. The output of the signal

generator driving the ADC analog input is bandpass filtered to

improve the harmonic distortion of the analog input signal. The

comparator on the evaluation board will convert the sine wave

CLK input signal to a square wave at TTL logic levels to drive

the sample clock input of the HI5805. The ADC data is

captured by a logic analyzer and then transferred over the GPIB

bus to the PC. The PC has the required software to perform the

Fast Fourier Transform (FFT) and do the data analysis.

Coherent testing is recommended in order to avoid the

inaccuracies of windowing. The sampling frequency and

analog input frequency have the following relationship: F

= M/N, where F

is the frequency of the input analog

sinusoid, F

is the sampling frequency, N is the number of

samples, and M is the number of cycles over which the

samples are taken. By making M an integer and odd number

(1, 3, 5, ...) the samples are assured of being nonrepetitive.

Refer to the HI5805 data sheet for a complete list of test

deﬁnitions and the results that can be expected using the

evaluation board with the test setup shown. Evaluating the

part with a reconstruction DAC is only suggested when

doing bandwidth or video testing.

HP8662A

FILTER

BANDPASS

HI5805EVAL1

PC OSCILLOSCOPE

HI5805

COMPARATOR

REF

CLK

DIGITAL DATA OUTPUT

GPIB

12-BIT DACDAS9200

EVALUATION BOARD

CLK

FIGURE 6. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM

TABLE 3. HI5805 PIN DESCRIPTION

PIN NO. NAME DESCRIPTION

1 CLK Input Clock

2DV

CC1

Digital Supply (5.0V)

GND1

Digital Ground

4DV

CC1

Digital Supply (5.0V)

GND1

Digital Ground

6AV

Analog Supply (5.0V)

GND

Analog Ground

IN+

Positive Analog Input

IN-

Negative Analog Input

10 V

DC Bias Voltage Output

11 V

ROUT

Reference Voltage Output

12 V

RIN

Reference Voltage Input

13 A

GND

Analog Ground

14 AV

Analog Supply (5.0V)

15 D11 Data Bit 11 Output (MSB)

16 D10 Data Bit 10 Output

17 D9 Data Bit 9 Output

18 D8 Data Bit 8 Output

19 D7 Data Bit 7 Output

20 D6 Data Bit 6 Output

21 D

GND2

Digital Output Ground

22 DV

CC2

Digital Output Supply (3.0V to 5.0V)

23 D5 Data Bit 5 Output

24 D4 Data Bit 4 Output

25 D3 Data Bit 3 Output

26 D2 Data Bit 2 Output

27 D1 Data Bit 1 Output

28 D0 Data Bit 0 Output (LSB)

Application Note 9707

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

HI5805EVAL1

Mfr. #:

Buy HI5805EVAL1

Manufacturer:

Renesas / Intersil

Description:

Data Conversion IC Development Tools HI5805 EVAL PL ATFORM

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