DS1220AB-200+

DS1220AB/AD
4 of 8
AC ELECTRICAL CHARACTERISTICS (T
A
: See Note 10)
(V
CC
= 5.0V ± 5% for DS1220AB)
(V
CC
= 5.0V ± 10% for DS1220AD)
PARAMETER SYMBOL
DS1220AB-100
DS1220AD-100
UNITS NOTES
MIN
MAX
Read Cycle Time
t
RC
100
ns
Access Time
t
ACC
100
ns
OE
to Output Valid
t
OE
50 ns
CE
to Output Valid
t
CO
100 ns
OE
or
CE
to Output Active
t
COE
5 ns 5
Output High Z from
Deselection
t
OD
35 ns 5
Output Hold from Address Change
t
OH
5
ns
Write Cycle Time
t
WC
100
ns
Write Pulse Width
t
WP
75
ns
3
Address Setup Time
t
AW
0
ns
Write Recovery Time
t
WR1
t
WR2
0
10
ns
ns
12
13
Output High from
WE
t
ODW
35 ns 5
Output Active from
WE
t
OEW
5 ns 4
Data Setup Time
t
DS
40
ns
4
Data Hold Time
t
DH1
t
DH2
0
10
ns
ns
12
13
DS1220AB/AD
5 of 8
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1220AB/AD
6 of 8
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (T
A
: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
1.5
µs
11
V
CC
slew from V
TP
to 0V t
F
300
µs
V
CC
slew from 0V to V
TP
t
R
300
µs
V
CC
Valid to
CE
and
WE
Inactive
t
PU
2 ms
V
CC
Valid to End of Write Protection t
REC
125 ms
(T
A
= +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time
t
DR
10
years
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the
battery backup mode.
NOTES:
1.
WE
is high for a read cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high-impedance state.
3. t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
CE
going low to the earlier of
CE
or
WE
going high.
4. t
DS
is measured from the earlier of
CE
or
WE
going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
CE
low transition occurs simultaneously with or later than the
WE
low transition, the output
buffers remain in a high-impedance state during this period.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in a high-impedance state during this period.

DS1220AB-200+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
NVRAM 16k Nonvolatile SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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