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LTC4240CGN#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LTC4240
16
4240f
A high to low transition on BD_SEL# causes the voltages
on the TIMER, GATE, 3V
OUT
, 5V
OUT
, 12V
OUT
and V
EEOUT
pins to begin ramping (see Figure 4). The TIMER pin
capacitance is charged by an 11.5µA current source while
the GATE capacitance is charged by a 65µA current source.
Concurrently, an internal charge pump turns on the gates
of the internal power switches that isolate the 12V and
–12V supplies. All faults are ignored during the time that
the voltage at the TIMER pin remains below 5.5V. In order
to avoid faults due to the charging of the bulk output
capacitors, all output voltages must settle before the
TIMER pin reaches 5.5V. See TIMER section for more
details.
The 5V
OUT
and 3V
OUT
supply outputs will ramp up accord-
ing to the slowest of the following slew rates:
dV
dt
A
C
or
II
C
a
or
II
C
b
LIMIT V LOAD V
LOAD VOUT
LIMIT V LOAD V
LOAD VOUT
=
µ
=
=
65
1
1
1
55
5
33
3
,
–
,()
–
()
() ()
()
() ()
()
stage in the hot plug sequence, indicating that the
LTC4240 is in reset mode with all power switches off
(BD_SEL# is still pulled high to long 5V).
The 12V and –12V supplies make contact at this stage.
Zener clamps Z1 and Z2 plus shunt RC snubbers R13-
C4 and R14-C5 help protect the 12V
IN
and V
EEIN
pins,
respectively, from large transient voltages during hot
insertion and short-circuit conditions.
The signal pins also connect at this point. This includes
the HEALTHY# signal connecting to the PWRGD pin
and the PCI_RST# signal connecting to the RESETIN
pin. The PWRGD and RESETIN signals are combined
internally with Bit 3 (C3) of the I
2
C command latch (see
Send Byte protocol) to generate the LOCAL_PCI_RST#
signal, which is available at the RESETOUT pin.
4. Short pins make contact. BD_SEL# signal connects to
the OFF/ON pin. This starts the electrical part of the
connection process. If the BD_SEL# signal is grounded
on the backplane, then the electrical connection pro-
cess starts immediately. Note that the electrical con-
nection process can be interrupted with the Send Byte
protocol of the I
2
C serial interface.
System backplanes that do not ground the BD_SEL#
signal will instead have circuitry that detects when
BD_SEL# has made contact with the plug-in board. The
backplane logic can then control the power up process
by pulling BD_SEL# low. Figure 4 illustrates the power
up sequence. The mating of BD_SEL# is represented by
the high to low transition of the BD_SEL# signal.
Power-Up Sequence
Two external N-channel power MOSFETs isolate the 3.3V
and 5V power paths, while two internal MOS switches
isolate the 12V and –12V power paths. (See front page
Application Circuit). Sense resistors R1 and R2 provide
current limit and fault detection for the 3V
IN
and 5V
IN
supplies, while R5 and C1 provide current control loop
compensation. Current fault detection for the 12V and
–12V supplies is done internally.
TIMER
10V/DIV
GATE
10V/DIV
12V
OUT
10V/DIV
V
EEOUT
10V/DIV
5V
OUT
10V/DIV
3V
OUT
10V/DIV
LCL_PCI_RST#
5V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
10ms/DIV
4240 F04
Figure 4. Normal Power-Up Sequence
APPLICATIO S I FOR ATIO
WUU
U
LTC4240
17
4240f
Note that capacitor C1 performs dual functions. In addi-
tion to controlling the ramp up rates of the 5V and 3.3V
outputs, it also compensates the current limit loop.
Current limit faults are ignored while the TIMER voltage is
less than 5.5V.
Once all four supplies are within tolerance, the PWRGD pin
(HEALTHY#) will be pulled low and LOCAL_PCI_RESET#
(RESETOUT) is free to follow PCI_RST#. Bit 3 of the I
2
C
command latch powers up low, thus not asserting
LOCAL_PCI_RST#.
Power-Down Sequence
When either BD_SEL# (OFF/ON) or Bit 2 of the command
latch (C2) is set high, a power-down sequence begins
(Figure 5).
The TIMER pin is immediately pulled low. The GATE pin
(Pin 19) is pulled down by a 200µA current source to
prevent the load currents on the 3.3V and 5V supplies from
going to zero instantaneously and glitching the power
supply voltages. Internal switches are connected to each
of the output supply voltage pins to discharge the output
bulk capacitors to ground. When any one of the output
voltages drops below its PWRGD threshold, the HEALTHY#
signal pulls high, LOCAL_PCI_RST# (RESETOUT) is as-
serted low, and the external status LED turns on.
Once the power-down sequence is complete the status
LED will light up and the CPCI card may be removed from
the slot. During extraction, the precharge circuit will
continue to bias the bus I/O pins at 1V until the long
connector pin connections are broken.
Early Power
Early Power usage is restricted by the CompactPCI (CPCI)
specification. It is intended to power up the precharge
circuit and I/O cells. The CPCI specification allows any of
the long power pins (5V, 3.3V, V(I/O)) to be used for Early
Power. Since Early Power is not isolated, a resistor should
be placed in series with each CPCI connector pin. Note that
if any Early Power pin is shorted on the inserted card, the
current limiting resistor will dissipate the power.
In order to maximize the DC current available from the 5V
supply, all eight 5V connector pins should be tied together
on the inserted card. The same applies to the ten 3.3V CPCI
connector pins. Early Power should then be drawn from
either or both of the two V(I/O) long pins. If either or both
of 5V and 3.3V is used for Early Power, then the 5V and
3.3V sense resistor values must be chosen such that the
1A/pin CPCI rule is not violated.
Connecting V
EEIN
To lessen the likelihood of faulting on power up, the V
EEOUT
output pin should be bypassed with a capacitor that is only
as large as necessary. A value of 10µF to 47µF is recom-
mended.
If a large value bypass capacitor is used (e.g.
≥100µF) on V
EEOUT
, current limit faults may occur during
power-up or during recovery from power failures.
TIMER
10V/DIV
GATE
10V/DIV
12V
OUT
10V/DIV
V
EEOUT
10V/DIV
5V
OUT
10V/DIV
3V
OUT
10V/DIV
LCL_PCI_RST#
5V/DIV
BD_SEL#
5V/DIV
HEALTHY#
5V/DIV
10ms/DIV
4240 F05
Figure 5. Normal Power-Down Sequence
APPLICATIO S I FOR ATIO
WUU
U
LTC4240
18
4240f
TIMER
5V/DIV
GATE
5V/DIV
12V
OUT
10V/DIV
V
EEOUT
10V/DIV
5V
OUT
10V/DIV
3V
OUT
10V/DIV
BD_SEL#
5V/DIV
FAULT
5V/DIV
10ms/DIV
4240 F06
Figure 6. Power-Up into a Short on 3.3V Output
Timer
During a power-up sequence, an 11.5µA current source is
connected to the TIMER pin (Pin 5) and charges up the
external TIMER pin capacitor. Current limit faults are
ignored until the TIMER voltage ramps to 5.5V. This feature
allows the LTC4240 to power-up CPCI boards with widely
varying capacitive loads on the back end supplies. The
power-up time for either of the two outputs under current
limit conditions is given by the slower of:
tXV
CXV
II
or a
t GATE
CXV V
A
b
ON OUT
LOAD XVOUT OUT
LIMIT XVOUT LOAD XVOUT
ON
OUT TH
()•
•
–
()
()
()
()
()
() ()
=
=
+
µ
22
1
65
2
Where XV
OUT
= 5V
OUT
or 3V
OUT
. The timer period should
be set longer than the maximum supply turn-on time but
short enough to not exceed the maximum safe operating
area of the pass transistor during a short-circuit. V
TH
is the
threshold voltage of the external power FET (2V – 3V). The
timer period will be:
t
CV
A
TIMER
TIMER
=
•
µ
55
11 5
.
.
(3)
The TIMER pin is immediately pulled low when either
OFF/ON (Pin 28) or Bit 2 of command latch (C2) goes high.
The TIMER pin also functions as a temporary auxiliary
supply for 12V
IN
. In the event of a large (greater than 1V)
glitch on 12V
IN
, the energy stored on the timer capacitor
is used as substitute 12V
IN
power. This improves the
glitch immunity of the LTC4240.
Thermal Shutdown
The internal switches for the 12V and –12V supplies are
protected by current limit and thermal shutdown circuits.
When the temperature of the die reaches 150°C, all four
switches will be latched off and the FAULT pin (Pin␣ 7) will
be pulled low. Since there is no automatic retry, power will
have to be cycled with the OFF/ON pin or the I
2
C command
latch.
Short-Circuit Protection
In order to lower power dissipation in the pass transistors
and to mitigate voltage spikes on the supplies during
short-circuit conditions, the current limit on each supply
is designed to be a function of the output voltage. As the
output voltage drops, the current limit decreases. Unlike a
traditional circuit breaker function where huge currents
can flow before the breaker trips, the current foldback
feature lowers short-circuit current by at least 50% when
powering up into a short.
If any supply is in current limit after the TIMER pin voltage
has ramped to 5.5V, then all four pass transistors will be
immediately turned off and FAULT will be asserted low
(Figure 6).
APPLICATIO S I FOR ATIO
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LTC4240CGN#TRPBF

Mfr. #:
Buy LTC4240CGN#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers CompactPCI Hot Swap Cntr w/ I2C Compatib
Lifecycle:
New from this manufacturer.
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