LTC4240
9
4240f
long pin must be connected to 3V
IN
to ensure precharge
output. See Input Transient Protection section.
3V
SENSE
(Pin 23): 3.3V Current Limit Sense. A sense
resistor placed between 3V
IN
and 3V
SENSE
determines the
current limit for this supply. A foldback feature makes the
current limit decrease as the voltage at the 3V
OUT
pin
approaches 0V. To disable current limit, 3V
SENSE
and 3V
IN
must be tied together.
3V
OUT
(Pin 24): 3.3V Output Sense. The PWRGD pin
cannot pull low until the 3V
OUT
pin voltage exceeds 2.9V.
If no 3.3V input supply is available, tie the 3V
OUT
pin to the
5V
OUT
pin. When the power switches are turned off, a
150Ω resistor pulls 3V
OUT
to ground.
V
EEOUT
(Pin 25): –12V Supply Output. An internal 1Ω
switch is connected between V
EEIN
and V
EEOUT
. V
EEOUT
must exceed –10.5V before the PWRGD pin pulls low.
When the power switches are turned off, a 650Ω resistor
pulls V
EEOUT
to ground.
12V
OUT
(Pin 26): 12V Supply Output. A 0.5Ω switch is
connected between 12V
IN
and 12V
OUT
. 12V
OUT
must
exceed 11.1V before the PWRGD pin can pull low. When
the power switches are turned off, a 430Ω resistor pulls
12V
OUT
to ground.
RESETIN (Pin 27): PCI Reset Input. Connect the CPCI
PCI_RST# signal to the RESETIN pin. Pulling RESETIN low
will cause RESETOUT to pull low. Note that the I
2
C
RESETIN latch output can also set RESETOUT. Do not
float.
OFF/ON (Pin 28): OFF/ON Input. Connect the CPCI
BD_SEL# signal to the OFF/ON pin. When the OFF/ON pin
is pulled low, the GATE pin is pulled high by a 65µA current
source and the internal 12V and –12V switches are turned
on. When the OFF/ON pin is pulled high, the GATE pin will
be pulled to ground by a 200µA current source and the 12V
and –12V switches turn off.
Cycling the OFF/ON pin high and low will reset a tripped
circuit breaker and start a new power-up sequence. The
I
2
C OFF/ON latch output can also be used to reset the
electronic circuit breaker. Do not float.
node. An external 1k resistor between the transistor’s base
and 3V
IN
is needed.
PRECHARGE (Pin 18): Precharge Monitor Input. An inter-
nal error amplifier servos the DRIVE pin voltage to keep the
precharge node at 1V. Becomes valid when long 5V and
3.3V power pins make contact .Tie pins 17 and 18 together
if precharge function is unused.
GATE (Pin 19): High Side Gate Drive for the External 3.3V
and 5V N-Channel Power Transistors. An external series
RC network is required for the current limit loop compen-
sation and to set the maximum ramp-up rate. During
power-up, the slope of the voltage rise at the GATE pin is
set by the 65µA current source charging the external GATE
capacitor or by the 3.3V or 5V current limit and the
associated output capacitor. During power-down, a 200µA
current source pulls the GATE pin to GND.
The voltage at the GATE pin will be modulated to maintain
a constant current when either the 3.3V or 5V supply goes
into current limit and the TIMER pin is less than 5.5V. Once
the TIMER pin is above 5.5V, and in the event of a current
fault condition lasting for longer than 35µs, the GATE pin
is immediately pulled to GND.
5V
SENSE
(Pin 20): 5V Current Limit Sense. A sense resistor
placed between 5V
IN
and 5V
SENSE
determines the current
limit for this supply. A foldback current feature makes the
current limit decrease as the voltage at the 5V
OUT
pin
approaches 0V. To disable the current limit, 5V
SENSE
and
5V
IN
must be tied together.
5V
IN
(Pin 21): 5V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 5V
IN
pin is less than 4.3V. At least
one long pin must be connected to 5V
IN
to ensure precharge
output. See Input Transient Protection section.
3V
IN
(Pin 22): 3.3V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 3V
IN
pin is less than 2.45V. If no
3.3V input supply is available, connect two series diodes
between 5V
IN
and 3V
IN
(tie anode of first diode to 5V
IN
and
cathode of second diode to 3V
IN
, Figure 15). At least one
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PI FU CTIO S
