Integrated Silicon Solution, Inc. - www.issi.com 1
Rev. A
10/22/09
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
IS42SM83200D / IS42SM16160D / IS42SM32800D
IS42RM83200D / IS42RM16160D / IS42RM32800D
32Mx8, 16Mx16, 8Mx32
256Mb Mobile Synchronous DRAM
OCTOBER 2009
FEATURES
Fully synchronous; all signals referenced to a •
positive clock edge
Internal bank for hiding row access and pre-•
charge
Programmable CAS latency: 2, 3•
Programmable Burst Length: 1, 2, 4, 8, and Full •
Page
Programmable Burst Sequence:•
Sequential and Interleave•
Auto Refresh (CBR)•
TCSR (Temperature Compensated Self Refresh) •
PASR (Partial Arrays Self Refresh): 1/16, 1/8, •
1/4, 1/2, and Full
Deep Power Down Mode (DPD)•
Driver Strength Control (DS): 1/4, 1/2, and Full•
OPTIONS
Configurations: •
- 32M x 8
- 16M x 16
- 8M x 32
Power Supply •
IS42SMxxx – V
d d /Vd d q = 3.3 V
IS42RMxxx – V
d d /Vd d q = 2.5 V
Packages: •
x8 / x16 –TSOP II (54), BGA (54) [x16 only]
x32 – TSOP II (86), BGA (90)
Temperature Range: •
Commercial (0°C to +70°C)
Industrial (–40 ºC to 85 ºC)
Parameter 32M x 8 16M x 16 8M x 32
Configuration 8M x 8 x 4 banks 4M x 16 x 4 banks 2M x 32 x 4 banks
Refresh Count 8K/64ms 8K/64ms 4K/64ms
Row Addressing A0-A12 A0-A12 A0-A11
Column Addressing A0-A9 A0-A8 A0-A8
Bank Addressing BA0, BA1 BA0, BA1 BA0, BA1
Precharge Addressing A10 A10 A10
ADDRESSING TABLE
DESCRIPTION
ISSI's 256Mb Mobile Synchronous DRAM achieves high-
speed data transfer using pipeline architecture. All input
and output signals refer to the rising edge of the clock
input. Both write and read accesses to the SDRAM are
burst oriented. The 256Mb Mobile Synchronous DRAM
is designed to minimize current consumption making it
ideal for low-power applications. Both TSOP and BGA
packages are offered, including industrial grade products.
KEY TIMING PARAMETERS
1. Available for x8/x16 only
2. Available for x32 only
Parameter -7
1
-75
2
-10 Unit
CLK Cycle Time
CAS Latency = 3
7 7.5 10 ns
CAS Latency = 2
9.6 9.6 12 ns
CLK Frequency
CAS Latency = 3
143 133 100 Mhz
CAS Latency = 2
104 104 83 Mhz
Access Time from CLK
CAS Latency = 3
5.4 5.4 8 ns
CAS Latency = 2
8 8 9 ns
