Data Sheet ADuM3210/ADuM3211
Rev. K | Page 17 of 21
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM3210/ADuM3211 digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at the input and output supply pins.
The capacitor value should be between 0.01 µF and 0.1 µF. The
total lead length between both ends of the capacitor and the
input power supply pin should not exceed 2 mm.
See the AN-1109 Application Note for board layout guidelines.
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x)
is highly dependent on system design, which varies widely by
application. The ADuM3210/ADuM3211 incorporate many
enhancements to make ESD reliability less dependent on system
design. The enhancements include
• ESD protection cells are added to all input/output interfaces.
• Key metal trace resistances are reduced using wider
geometry and paralleling of lines with vias.
• The SCR effect inherent in CMOS devices is minimized
by use of a guarding and isolation technique between the
PMOS and NMOS devices.
• Areas of high electric field concentration are eliminated
using 45° corners on metal traces.
• Supply pin overvoltage is prevented with larger ESD clamps
between each supply pin and its respective ground.
Although the ADuM3210/ADuM3211 improve system-level
ESD reliability, they are no substitute for a robust system-level
design. For detailed recommendations on board layout and
system-level design, see the AN-793 Application Note, ESD/
Latch-Up Considerations with iCoupler Isolation Products.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propaga-
tion delay to a logic low output can differ from the propagation
delay to a logic high output.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
06866-009
Figure 12. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM3210/ADuM3211 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM3210/
ADuM3211 components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 2 µs, a periodic set
of refresh pulses indicative of the correct input state is sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than approximately 5 µs, the input side
is assumed to be unpowered or nonfunctional, and the isolator
output is forced to a default state by the watchdog timer circuit
(see Table 34 and Table 35).
The ADuM3210/ADuM3211 are immune to external magnetic
fields. The limitation on the magnetic field immunity of the
ADuM3210/ADuM3211 is set by the condition in which induced
voltage in the receiving coil of the transformer is sufficiently large
to either falsely set or reset the decoder. The following analysis
defines the conditions under which this can occur. The 3 V oper-
ating condition of the ADuM3210/ADuM3211 is examined
because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil
is given by
V = (−dβ/dt) ∑ πr
n
2
; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
r
n
is the radius of the n
th
turn in the receiving coil (cm).
N is the total number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM3210/
ADuM3211 and an imposed requirement that the induced voltage
be, at most, 50% of the 0.5 V margin at the decoder, a maximum
allowable magnetic field is calculated as shown in Figure 13.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
06866-010
Figure 13. Maximum Allowable External Magnetic Flux Density
