LTC2461/LTC2463
10
24613fa
APPLICATIONS INFORMATION
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is consid-
ered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and
is used for reading from the device before the initiation
of a new conversion.
Data Transferring
After the START condition, the I
2
C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NAK) by leaving the
SDA line HIGH impedance (the external pull-up resistor
will hold the line HIGH). Change of data only occurs while
the clock line (SCL) is LOW.
Output Data Format
After a START condition, the master sends a 7-bit address
followed by a read request (R) bit. The bit R is 1 for a
Read Request. If the 7-bit address matches the LTC2461/
LTC2463’s address (0010100 or 1010100, depending on the
state of the pin A0) the ADC is selected. When the device is
addressed during the conversion state, it does not accept
the request and issues a NAK by leaving the SDA line HIGH.
If the conversion is complete, the LTC2461/LTC2463 issue
an ACK by pulling the SDA line LOW.
Following the ACK, the LTC2461/LTC2463 can output data.
The data output stream is 16 bits long and is shifted out
on the falling edges of SCL (see Figure 5a).
The DATA INPUT/OUTPUT state is concluded once all 16
data bits have been read or after a STOP condition.
The LTC2463 (differential input) output code is given by
32768 • (V
IN
+
– V
IN
–
)/V
REF
+ 32768. The first bit output
by the LTC2463, D15, is the MSB, which is 1 for V
IN
+
≥
V
IN
–
and 0 for V
IN
+
< V
IN
–
. This bit is followed by succes-
sively less significant bits (D14, D13, …) until the LSB is
output by the LTC2463, see Table 1.
The LTC2461 (single-ended input) output code is a direct
binary encoded result, see Table 1.
D8D13D14
MSB
D15RSDA
SCL
7-BIT
ADDRESS
START BY
MASTER
D7 D6 D5 D0
LSB
ACK BY
MASTER
NACK BY
MASTER
SLEEP DATA OUTPUT CONVERSION
24613 F05a
ACK BY
LTC2461/LTC2463
Figure 5a. Read Sequence Timing Diagram