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PI6C185-00QIE

P1-P3P4-P6P7-P7
PI6C185-00
Precision 1-7 Clock Buffer
4
PS8317F 11/13/08
SDRAM Clock Buffer Operating Specification
AC Timing
DC Operating Specifications (V
DD
= +3.3V ±5%, T
A
= 0°C - 70°C)
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DD
0.2V
DD
3.0+
V
V
LI
egatlovwoltupnIV
SS
3.0-8.0
I
LI
tnerrucegakaeltupnIV<0
NI
V<
DD
5-5+Am
V
DD
%5±V3.3=]9-0[
V
HO
egatlovhgihtuptuOI
HO
Am1–=4.2
V
V
LO
egatlovwoltuptuOI
LO
Am1=4.0
C
TUO
ecnaticapacniptuptuO 6
Fp
C
NI
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L
NIP
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T
A
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I
NIMHO
tnerrucpu-lluPV
TUO
V0.2=45–
Am
I
XAMHO
tnerrucpu-lluPV
TUO
V531.3=64-
I
NIMLO
tnerrucnwod-lluPV
TUO
V0.1=45
I
XAMLO
tnerrucnwod-lluPV
TUO
V4.0=35
t
hr
MARDSylnoMARDSetaregdeesirtuptuOV4.2-V40@%5±V3.35.14
sn/V
t
ht
MARDSylnoMARDSetaregdellaftuptuOV4.0-V4.2@%5±V3.35.14
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t
PKDS
doirepKLCMARDS0.515.510.015.015.70.8
sn
t
HKDS
emithgihKLCMARDS6.53.32.2
t
LKDS
emitwolKLCMARDS3.51.30.2
t
ESIRDS
emitesirKLCMARDS5.10.45.10.44.10.4
sn/V
t
LLAFDS
emitllafKLCMARDS5.10.45.10.44.10.4
t
HLP
yaledporpHLreffuBMARDS0.10.50.10.50.10.5
sn
t
LHP
yaledporpLHreffuBMARDS0.10.50.10.50.10.5
t
LZP
t,
HZP
yaledelbanEreffuBMARDS0.10.80.10.80.10.8
t
ZLP
t,
ZHP
yaledelbasiDreffuBMARDS0.10.80.10.80.10.8
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t
WKSDS
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08-0298
PI6C185-00
Precision 1-7 Clock Buffer
5
PS8317F 11/13/08
1.5V 1.5V
t
phl
t
plh
1.5V 1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
t
SDFALL
t
SDRISE
Test Load
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500-ohm resistor in parallel.
Minimum and Maximum Expected Capacitive Loads
Design Guidelines to Reduce EMI
1. Place series R
S
resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. R
S
Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
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MARDS0203Fp
MMIDMARDS
noitacificepS
08-0298
PI6C185-00
Precision 1-7 Clock Buffer
6
PS8317F 11/13/08
PCB Layout Suggestion
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C1-C5 should be placed as close as possible to
their respective V
DD
.
Recommended capacitor values:
C1-C5 .............. 0.1μF, ceramic
C6 .................. 22μF
Figure 2. Design Guidelines
C1
C2
C3
C5
C4
FB
V
DD
C6
22mF
Via to
V
SS Plane
Via to
V
DD Plane
Void in Power Plane
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
PI6C185
R
7
CL
SDRAM
DIMM
Spec.
From
Chipset
s
08-0298
P1-P3P4-P6P7-P7

PI6C185-00QIE

Mfr. #:
Buy PI6C185-00QIE
Manufacturer:
Diodes Incorporated
Description:
Clock Buffer Precision 1:7 Clock Driver
Lifecycle:
New from this manufacturer.
Delivery:
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