5
FN2853.7
September 4, 2015
current capability of the ICL7667 enables it to drive a
1000pF load with a rise time of only 40ns. Because the
output stage impedance is very low, up to 300mA will flow
through the series N-Channel and P-Channel output devices
(from V+ to V-) during output transitions. This crossover current
is responsible for a significant portion of the internal power
dissipation of the ICL7667 at high frequencies. It can be
minimized by keeping the rise and fall times of the input to the
ICL7667 below 1µs.
Application Notes
Although the ICL7667 is simply a dual level-shifting inverter,
there are several areas to which careful attention must be
paid.
Grounding
Since the input and the high current output current paths
both include the V- pin, it is very important to minimize and
common impedance in the ground return. Since the ICL7667
is an inverter, any common impedance will generate
negative feedback, and will degrade the delay, rise and fall
times. Use a ground plane if possible, or use separate
ground returns for the input and output circuits. To minimize
any common inductance in the ground return, separate the
input and output circuit ground returns as close to the
ICL7667 as is possible.
Bypassing
The rapid charging and discharging of the load capacitance
requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance
over a wide frequency range should be used. A 4.7µF
tantalum capacitor in parallel with a low inductance 0.1µF
capacitor is usually sufficient bypassing.
Output Damping
Ringing is a common problem in any circuit with very fast
rise or fall times. Such ringing will be aggravated by long
inductive lines with capacitive loads. Techniques to reduce
ringing include:
• Reduce inductance by making printed circuit board traces
as short as possible.
• Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
• Use a 10 to 30 resistor in series with the output of the
ICL7667. Although this reduces ringing, it will also slightly
increase the rise and fall times.
• Use good by-passing techniques to prevent supply
voltage ringing.
Power Dissipation
The power dissipation of the ICL7667 has three main
components:
1. Input inverter current loss
2. Output stage crossover current loss
3. Output stage I
2
R power loss
The sum of the above must stay within the specified limits for
reliable operation.
As noted above, the input inverter current is input voltage
dependent, with an I
V+
of 0.1mA maximum with a logic 0
input and 6mA maximum with a logic 1 input.
The output stage crowbar current is the current that flows
through the series N-Channel and P-Channel devices that
form the output. This current, about 300mA, occurs only
during output transitions. Caution: The inputs should never
be allowed to remain between V
IL
and V
IH
since this could
leave the output stage in a high current mode, rapidly
leading to destruction of the device. If only one of the drivers
is being used, be sure to tie the unused input to V- or
ground. NEVER leave an input floating. The average supply
current drawn by the output stage is frequency dependent,
as can be seen in Figure 5 (I
V+
vs Frequency graph in the
Typical Characteristics Graphs).
The output stage I
2
R power dissipation is nothing more than
the product of the output current times the voltage drop
across the output device. In addition to the current drawn by
any resistive load, there will be an output current due to the
charging and discharging of the load capacitance. In most
high frequency circuits the current used to charge and
discharge capacitance dominates, and the power dissipation
is approximately:
where C = Load Capacitance, f = Frequency
In cases where the load is a power MOSFET and the gate
drive requirement are described in terms of gate charge, the
ICL7667 power dissipation will be:
where Q
G
= Charge required to switch the gate, in
Coulombs, f = Frequency.
Power MOS Driver Circuits
Power MOS Driver Requirements
Because it has a very high peak current output, the ICL7667
the at driving the gate of power MOS devices. The high
current output is important since it minimizes the time the
power MOS device is in the linear region. Figure 9 is a
typical curve of Charge vs Gate voltage for a power
MOSFET. The flat region is caused by the Miller
capacitance, where the drain-to-gate capacitance is
multiplied by the voltage gain of the FET. This increase in
capacitance occurs while the power MOSFET is in the linear
region and is dissipating significant amounts of power. The
very high current output of the ICL7667 is able to rapidly
ICL7667
