74ACT323PC

June 1988
Revised October 1998
74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
© 1999 Fairchild Semiconductor Corporation DS009787.prf www.fairchildsemi.com
74ACT323
8-Bit Universal Shift/Storage Register with
Synchronous Reset and Common I/O Pins
General Description
The ACT323 is an 8-bit universal shift/storage register with
3-STATE outputs. Parallel load inputs and flip-flop outputs
are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q
0
and Q
7
to allow
easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
Features
I
CC
and I
OZ
reduced by 50%
Common parallel I/O for reduced pin count
Additional serial inputs and outputs for expansion
Four operating modes: shift left, shift right, load and
store
3-STATE outputs for bus-oriented applications
Outputs source/sink 24 mA
TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols Connection Diagram
Pin Assignment
for DIP
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACT323PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Name Description
CP Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0
, S
1
Mode Select Inputs
SR
Synchronous Reset Input
OE
1
, OE
2
3-STATE Output Enable Inputs
I/O
0
–I/O
7
Multiplexed Parallel Data Inputs or
3-STATE Parallel Data Outputs
Q
0
, Q
7
Serial Outputs
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74ACT323
Functional Description
The ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0
and S
1
as shown
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR
overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Mode Select Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Inputs Response
SR
S
1
S
0
CP
LXX
Synchronous Reset; Q
0
–Q
7
= LOW
HHH
Parallel Load; I/O
n
Q
n
HLH Shift Right; DS
0
Q
0
, Q
0
Q
1
, etc.
HH L
Shift Left; DS
7
Q
7
, Q
7
Q
6
, etc.
H L L X Hold
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74ACT323
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

74ACT323PC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Counter Shift Registers 8-Bit Shift/Stor Reg
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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