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ADCMP551BRQ

P1-P3P4-P6P7-P9P10-P12P13-P15
Single-Supply, High Speed
PECL/LVPECL Comparators
Data Sheet
ADCMP551/ADCMP552/ADCMP553
Rev. B Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Single power supply
500 ps propagation delay input to output
125 ps overdrive dispersion
Differential PECL/LVPECL compatible outputs
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 70 dB
700 ps minimum pulse width
Equivalent input rise time bandwidth > 750 MHz
Typical output rise/fall of 500 ps
Programmable hysteresis
APPLICATIONS
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
Disk drive read channel detection
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The ADCMP551/ADCMP552/ADCMP553 are single-supply,
high speed comparators fabricated on Analog Devices, Inc.,
proprietary XFCB process. The devices feature a 500 ps
propagation delay with less than 125 ps overdrive dispersion.
Overdrive dispersion, a measure of the difference in propagation
delay under differing overdrive conditions, is a particularly
important characteristic of high speed comparators. A separate
programmable hysteresis pin is available on the ADCMP552.
A differential input stage permits consistent propagation delay
with a common-mode range from −0.2 V to VCCI − 2.0 V. Outputs
are complementary digital signals and are fully compatible with
PECL and 3.3 V LVPECL logic families. The outputs provide
sufficient drive current to directly drive transmission lines
terminated in 50 Ω to VCCO − 2 V. A latch input is included
and permits tracking, track-and-hold, or sample-and-hold
modes of operation. The latch input pins contain internal pull-
ups that set the latch in tracking mode when left open.
The ADCMP551/ADCMP552/ADCMP553 are specified over
the −40°C to +85°C industrial temperature range. The ADCMP551
is available in a 16-lead QSOP package; the ADCMP552 is available
in a 20-lead QSOP package; and the ADCMP553 is available in
an 8-lead MSOP package.
04722-001
NONINVERTING
INPUT
INVERTING
INPUT
LATCH ENABLE
INPUT
Q OUTPUT
LATCH ENABLE
INPUT
Q OUTPUT
ADCMP551/
ADCMP552/
ADCMP553
*ADCMP552 ONLY
HYS*
ADCMP551/ADCMP552/ADCMP553 Data Sheet
Rev. B | Page 2 of 15
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Considerations .............................................................. 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Timing Information ....................................................................... 10
Applications Information .............................................................. 11
Clock Timing Recovery ............................................................. 11
Optimizing High Speed Performance ..................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 12
Minimum Input Slew Rate Requirement ................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
3/15—Rev. A to Rev. B
Changed ADCMP55x to
ADCMP551/ADCMP552/ADCMP553 ..................... Throughout
Changes to Table 3 ............................................................................ 6
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
6/13—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
10/04—Revision 0: Initial Version
Data Sheet ADCMP551/ADCMP552/ADCMP553
Rev. B | Page 3 of 15
SPECIFICATIONS
V
CCI
= 3.3 V, V
CCO
= 3.3 V, T
A
= 25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Input Voltage Range −0.2 V
CCI
− 2.0 V
Input Differential Voltage Range −3 +3 V
Input Offset Voltage V
OS
−IN = 0 V, +IN = 0 V −10.0 ±2.0 +10.0 mV
Input Offset Voltage Channel Matching ±1.0 mV
Offset Voltage Tempco ΔV
OS
/d
T
2.0 μV/°C
Input Bias Current I
IN
−IN = −0.2 V, +IN = +1.3 V −28.0 −6.0 +5.0 μA
Input Bias Current Tempco −5.0 nA/°C
Input Offset Current −3.0 ±1.0 +3.0 μA
Input Capacitance C
IN
1.0 pF
Input Resistance, Differential Mode 1800 kΩ
Input Resistance, Common Mode 1000 kΩ
Active Gain A
V
60 dB
Common-Mode Rejection Ratio CMRR V
CM
= −0.2 V to +1.3 V 76 dB
Hysteresis R
HYS
= ∞ ±0.5 mV
LATCH ENABLE CHARACTERISTICS
Latch Enable Voltage Range
V
CCI
− 1.8 V
CCI
− 0.8 V
Latch Enable Differential Voltage Range 0.4 1.0 V
Latch Enable Input High Current @ V
CCI
− 0.8 V −150 +150 μA
Latch Enable Input Low Current @ V
CCI
− 1.8 V −150 +150 μA
LE Voltage, Open Latch inputs not connected V
CCI
− 0.15 V
CCI
V
LE Voltage, Open
Latch inputs not connected V
CCI
/2 − 0.075 V
CCI
/2 + 0.075 V
Latch Setup Time t
S
V
OD
= 250 mV 100 ps
Latch Hold Time t
H
V
OD
= 250 mV 100 ps
Latch to Output Delay t
PLOH
, t
PLOL
V
OD
= 250 mV 450 ps
Latch Minimum Pulse Width t
PL
V
OD
= 250 mV 700 ps
DC OUTPUT CHARACTERISTICS
Output Voltage—High Level V
OH
PECL 50 Ω to V
DD
− 2.0 V V
CCO
− 1.15 V
CCO
− 0.78 V
Output Voltage—Low Level V
OL
PECL 50 Ω to V
DD
− 2.0 V V
CCO
− 2.00 V
CCO
− 1.54 V
AC OUTPUT CHARACTERISTICS
Rise Time t
R
10% to 90% 510 ps
Fall Time t
F
10% to 90% 490 ps
AC OUTPUT CHARACTERISTICS (ADCMP553)
Rise Time t
R
10% to 90% 440 ps
Fall Time t
F
10% to 90% 410 ps
AC PERFORMANCE
Propagation Delay t
PD
V
OD
= 1 V 500 ps
V
OD
= 20 mV 625 ps
Propagation Delay Tempco Δt
PD
/d
T
V
OD
= 1 V 0.25 ps/°C
Prop Delay Skew—Rising Transition to
Falling Transition
V
OD
= 1 V 35 ps
Within Device Propagation Delay
Skew—Channel-to-Channel
V
OD
= 1 V 35 ps
Overdrive Dispersion 20 mV ≤ V
OD
≤ 100 mV 75 ps
Overdrive Dispersion 50 mV ≤ V
OD
≤ 1.0 V 75 ps
Slew Rate Dispersion 0.4 V/ns ≤ SR ≤ 1.33 V/ns 75 ps
P1-P3P4-P6P7-P9P10-P12P13-P15

ADCMP551BRQ

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Manufacturer:
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Description:
Analog Comparators SGL - Supply High Speed PECL
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