ADCMP552BRQ Datasheet ADCMP553BRMZ, ADCMP552BRQZ, ADCMP551BRQZ | P4-P6

ADCMP551/ADCMP552/ADCMP553 Data Sheet

Rev. B | Page 4 of 15

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE (continued)

Pulse Width Dispersion 700 ps ≤ PW ≤ 10 ns 25 ps

Duty Cycle Dispersion 33 MHz, 1 V/ns, V

= 0.5 V 10 ps

Common-Mode Voltage Dispersion 1 V swing, 0.3 V ≤ V

≤ 0.8 V 10 ps

Equivalent Input Rise Time Bandwidth

0 V to 1 V swing, 2 V/ns 750 MHz

Maximum Toggle Rate >50% output swing 800 MHz

Minimum Pulse Width PW

MIN

Δt

< 25 ps 700 ps

RMS Random Jitter

= 250 mV, 1.3 V/ns,

500 MHz, 50% duty cycle

1.1 ps

Unit-to-Unit Propagation Delay Skew 50 ps

POWER SUPPLY (ADCMP551/ADCMP552)

Input Supply Current I

VCCI

@ 3.3 V 8 12 17 mA

Output Supply Current I

VCCO

@ 3.3 V without load 3 5 9 mA

Output Supply Current @ 3.3 V with load 40 55 70 mA

Input Supply Voltage V

CCI

Dual 3.135 3.3 5.25 V

Output Supply Voltage V

CCO

Dual 3.135 3.3 5.25 V

Positive Supply Differential V

CCO

− V

CCI

−0.2 +2.3 V

Power Dissipation P

Dual, without load 40 55 75 mW

Power Dissipation Dual, with load 90 110 130 mW

DC Power Supply Rejection Ratio—V

CCI

PSRR

VCCI

75 dB

DC Power Supply Rejection Ratio—V

CCO

PSRR

VCCO

85 dB

POWER SUPPLY (ADCMP553)

Positive Supply Current I

VCC

@ 3.3 V without load 9 13 mA

Positive Supply Current @ 3.3 V with load 35 42 mA

Positive Supply Voltage V

Dual 3.135 3.3 5.25 V

Power Dissipation P

Dual, without load 30 42 mW

Power Dissipation Dual, with load 60 75 mW

DC Power Supply Rejection Ratio—V

PSRR

VCC

70 dB

HYSTERESIS (ADCMP552 Only)

Programmable Hysteresis 0 40 mV

Equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: BW

= .22/ (tr

COMP

− tr

where tr

is the 20/80 input transition time applied to the comparator and tr

COMP

is the effective transition time as digitized by the comparator input.

Data Sheet ADCMP551/ADCMP552/ADCMP553

Rev. B | Page 5 of 15

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages

Input Supply Voltage (V

CCI

to GND) −0.5 V to +6.0 V

Output Supply Voltage (V

CCO

to GND) −0.5 V to +6.0 V

Ground Voltage Differential −0.5 V to +0.5 V

Input Voltages

Input Common-Mode Voltage −0.5 V to +3.5 V

Differential Input Voltage −4.0 V to +4.0 V

Input Voltage, Latch Controls −0.5 V to +5.5 V

Output

Output Current 30 mA

Temperature

Operating Temperature, Ambient −40°C to +85°C

Operating Temperature, Junction 125°C

Storage Temperature Range −65°C to +150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL CONSIDERATIONS

The ADCMP551 16-lead QSOP package has a θ

(junction-to-

ambient thermal resistance) of 104°C/W in still air.

The ADCMP552 20-lead QSOP package has a θ

(junction-to-

ambient thermal resistance) of 80°C/W in still air.

The ADCMP553 8-lead MSOP package has a θ

(junction-to-

ambient thermal resistance) of 130°C/W in still air.

ESD CAUTION

ADCMP551/ADCMP552/ADCMP553 Data Sheet

Rev. B | Page 6 of 15

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 2. ADCMP551 16-Lead QSOP

Pin Configuration

Figure 3. ADCMP552 20-Lead QSOP

Pin Configuration

Figure 4. ADCMP553 8-Lead MSOP

Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic Description ADCMP551 ADCMP552 ADCMP553

3, 14 1, 4, 17, 20 V

CCO

Logic Supply Terminal.

1 2 6 QA

One of Two Complementary Outputs for Channel A. QA is logic high if the

analog voltage at the noninverting input is greater than the analog voltage at

the inverting input (provided the comparator is in the compare mode). See the

description of Pin LEA for more information.

2 3 5

One of Two Complementary Outputs for Channel A. QA is logic low if the analog

voltage at the noninverting input is greater than the analog voltage at the

inverting input (provided the comparator is in the compare mode). See the

description of Pin LEA for more information.

4 5 2 LEA

One of Two Complementary Inputs for Channel A Latch Enable. In compare

mode (logic high), the output tracks changes at the input of the comparator. In

latch mode (logic low), the output reflects the input state just prior to the

comparator being placed into latch mode. LEA must be driven in conjunction

with LEA.

5 6 1

LEA

One of Two Complementary Inputs for Channel A Latch Enable. In compare

mode (logic low), the output tracks changes at the input of the comparator. In

latch mode (logic high), the output reflects the input state just prior to the

comparator being placed into latch mode. LEA must be driven in conjunction

with LEA

6 7 V

CCI

Input Supply Terminal.

7 8 4 −INA

Inverting Analog Input of the Differential Input Stage for Channel A. The

inverting A input must be driven in conjunction with the noninverting A input.

8 9 3 +INA

Noninverting Analog Input of the Differential Input Stage for Channel A. The

noninverting A input must be driven in conjunction with the inverting A input.

10 HYSA Programmable Hysteresis.

11 HYSB Programmable Hysteresis.

9 12 +INB

Noninverting Analog Input of the Differential Input Stage for Channel B. The

noninverting B input must be driven in conjunction with the inverting B input.

10 13 −INB

Inverting Analog Input of the Differential Input Stage for Channel B. The

inverting B input must be driven in conjunction with the noninverting B input.

11 14 8 AGND Analog Ground.

12 15

LEB

One of Two Complementary Inputs for Channel B Latch Enable. In compare

mode (logic low), the output tracks changes at the input of the comparator. In

latch mode (logic high), the output reflects the input state just prior to the

comparator being placed into latch mode. LEB must be driven in conjunction

with LEB

04722-002

ADCMP551

TOP VIEW

(Not to Scale)

–INA

+INA

CCO

CCI

LEA

–INB

+INB

CCO

AGND

LEB

04722-003

ADCMP552

TOP VIEW

(Not to Scale)

–INA

CCO

CCI

LEA

CCO

+INA

HYS

–INB

CCO

AGND

LEB

CCO

+INB

HYSB

04722-004

ADCMP553

TOP VIEW

(Not to Scale)

LEA

+INA

–INA

AGND

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

ADCMP552BRQ

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog Comparators SGL - Supply High Speed PECL

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ADCMP552BRQ

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