Rev B 11/17/15 4 FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR
844071 DATA SHEET
Table 3D. LVDS DC Characteristics, V
DD
= 3.3V ± 10%, T
A
= 0°C to 70°C
Table 3E. LVDS DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Table 4. Crystal Characteristics
NOTE: It is not recommended to overdrive the crystal input with an external clock source.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 275 365 455 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.125 1.3 1.55 V
V
OS
V
OS
Magnitude Change 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 205 335 465 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 0.89 1.2 1.48 V
V
OS
V
OS
Magnitude Change 50 mV
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 20.833 28.3 MHz
Equivalent Series Resistance (ESR) 50
Shunt Capacitance 7pF
Drive Level 1mW
FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR 5 Rev B 11/17/15
844071 DATA SHEET
AC Electrical Characteristics
Table 5A. AC Characteristics, V
DD
= 3.3V ± 10%, T
A
= 0°C to 70°
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Refer to the Phase Noise Plot.
Table 5B. AC Characteristics, V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Refer to the Phase Noise Plot.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 62.5 170 MHz
tjit(Ø)
RMS Phase Jitter,
Random; NOTE 1
150MHz,
Integration Range: 900kHz – 7.5MHz
0.45 ps
75MHz,
Integration Range: 900kHz – 7.5MHz
0.46 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 150 400 ps
odc Output Duty Cycle 48 52 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 62.5 170 MHz
tjit(Ø)
RMS Phase Jitter,
Random; NOTE 1
150MHz,
Integration Range: 900kHz – 7.5MHz
0.56 ps
75MHz,
Integration Range: 900kHz – 7.5MHz
0.60 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 150 400 ps
odc Output Duty Cycle 48 52 %
Rev B 11/17/15 6 FEMTOCLOCK® CRYSTAL-TO-LVDS CLOCK GENERATOR
844071 DATA SHEET
Typical Phase Noise at 150MHz (3.3V)
Raw Phase Noise Data
150MHz
RMS Phase Jitter (Random)
900kHz to 7.5MHz = 0.45ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M

844071AGLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products SATA & SAS FemtoClk Synthesizer LVDS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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