46
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
Figure 27. Echo Read Clock & Read Enable Operation in Double Data Rate Mode (IDT Standard Mode Only)
RCLK
REN
EREN
ERCLK
EF
RCS
t
ENS
t
REF
t
ERCLK
t
ENH
Qn
t
ENS
t
ENH
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
t
OLZ
t
A
t
A
t
CLKEN
t
A
t
OLZ
t
OLZ
t
A
t
A
t
A
t
A
t
A
W
D-10
W
D-9
W
D-8
W
D-6
W
D-5
W
D-4
W
D-3
W
D-2
Last Word W
D
5996 drw30
t
CLKEN
t
A
W
D-7
W
D-6
t
A
W
D-1
t
ENS
NO Read NO Read
NOTES:
1. The EREN output is “or gated” to RCS and REN and will follow these inputs provided that the FIFO is not empty. If the FIFO is empty, EREN will go HIGH to indicate that there is no new word available.
2. The EREN output is synchronous to RCLK.
3. OE = LOW.
4. The truth table for EREN is shown below:
RCLK EF RCS REN EREN
1000
1011
1101
1111
0XX1
47
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
Figure 28. Echo RCLK and Echo
RENREN
RENREN
REN
Operation (FWFT Mode Only)
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c. Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
d. EREN goes HIGH, no new word has been placed on the output register on this cycle.
e. No Operation.
f. RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
g. REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
h. Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
i. This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
3. OE is LOW.
4. The truth table for EREN is shown below:
Qn
O/P
Reg.
t
A
t
REF
OR
5996 drw31
t
RCSLZ
REN
t
ENS
t
ENH
RCS
t
ENS
RCLK
a
b
c
d
e
f
g
h
i
W
n+1
WCLK
WEN
D0 - Dn
t
SKEW1
t
ENS
t
DS
t
ENH
W
n+2
W
n+3
ERCLK
EREN
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
W
n+1
W
n+2
W
n+3
t
A
t
REF
W
n+1
W
n+2
W
n+3
t
A
W
n
Last Word
t
A
t
A
t
DH
t
DH
t
DH
t
DS
t
DS
1
2
t
ERCLK
HIGH-Z
RCLK OR RCS REN EREN
0000
0011
0101
0111
1XX1
48
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard mode: if x20 Input or x20 Output bus Width is selected, D = 32,768 for the IDT72T2098, 65,536 for the IDT72T20108, 131,072 for the IDT72T20118, 262,144 for
the IDT72T20128. If both x10 Input and x10 Output bus Widths are selected, D = 65,536 for the IDT72T2098, 131,072 for the IDT72T20108, 262,144 for the IDT72T20118, 524,288
for the IDT72T20128.
In FWFT mode: if x20 Input or x20 Output bus Width is selected, D = 32,769 for the IDT72T2098, 65,537 for the IDT72T20108, 131,073 for the IDT72T20118, 262,145 for the IDT72T20128.
If both x10 Input and x10 Output bus Widths are selected, D = 65,537 for the IDT72T2098, 131,073 for the IDT72T20108, 262,145 for the IDT72T20118, 524,289 for the IDT72T20128.
3. PAF is asserted and updated on the rising edge of WCLK only.
4. tSKEW3 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW3, then the PAF deassertion time may be delayed one extra WCLK cycle.
5. RCS = LOW.
Figure 29. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted and updated on the rising edge of RCLK only.
5.
tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then the PAE deassertion may be delayed one extra RCLK cycle.
6. RCS = LOW.
Figure 30. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAF
RCLK
REN
5996 drw32
1
2
12
D-(m+1) words
in FIFO
(2)
D - m words in FIFO
(2)
D - (m +1) words in FIFO
(2)
t
ENH
t
ENS
t
PAFS
t
ENS
t
ENH
t
CLKL1
t
SKEW3
(3)
t
PAFS
t
CLKL1
WCLK
WEN
PAE
RCLK
12 12
REN
5996 drw33
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
t
ENS
t
SKEW3
(4)
t
ENH
t
PAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
t
PAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
t
ENS
t
ENH
t
CLKH1
t
CLKL1

IDT72T20118L4BB

Mfr. #:
Manufacturer:
Description:
IC FIFO 65536X20 4NS 208BGA
Lifecycle:
New from this manufacturer.
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