41
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
FEBRUARY 13, 2009
Figure 21. Read Cycle and Read Chip Select Timing (FWFT Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is
less than t
SKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
4. D = 16,385 for IDT72T2098, 32,769 for IDT72T20108, 65,537 for IDT72T20118, 131,073 for IDT72T20128.
5. OE = LOW.
6. RCLK must be free running for EF to update.
WCLK
12
WEN
D0 - Dn
RCLK
REN
Q0 - Qn
PAF
IR
t
PAFS
t
WFF
t
WFF
5996 drw24
PAE
OR
W
1
W
2
W
3
W
m+2
W
[m+3]
t
RCSHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
A
t
A
t
ENS
RCS
t
SKEW2
W
D
t
PAES
W
[D-n]
W
[D-n-1]
t
A
t
A
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
t
ENS
1
t
ENS
t
RCSLZ
t
ENS
t
REF
D-1
+ 1
][
W
2
D-1
+ 2
][
W
2
t
ENH
