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9FGU0641AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15
OCTOBER 18, 2016 7 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0641 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
Electrical Characteristics–DIF Output Phase Jitter Parameters
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope averaging on fast setting 1.2 2.4 3.6
V/ns
1,2,3
Scope averaging on slow setting 0.8 1.7 2.5
V/ns
1,2,3
Slew rate matching
Δ
Trf Slew rate matching, Scope averaging on 9 20
%
1,2,4
Voltage High V
HIGH
600 750 850 7
Voltage Low V
LOW
-150 26 150 7
Max Voltage Vmax 763 1150 7
Min Voltage Vmin -300 22 7
Vswing Vswing Scope averaging off 300 1448 mV 1,2,7
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 390 550 mV 1,5,7
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 11 140 mV 1,6,7
2
Measured from differential waveform
7
At default SMBus amplitude settin
g
s.
Slew rate Trf
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
Δ
-Vcross to be smaller than Vcross absolute.
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production.
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
IND.
LIMIT
UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 27.7 40 86 ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.0 1.3 3
ps
(rms)
1,2,3,5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
1.9
2.2 3.1
ps
(rms)
1,2,3,5
t
jphPCIeG3
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.4
0.6 1
ps
(rms)
1,2,3,5
t
jphPCIeG3SRn
S
PCIe Gen 3 Separate Reference No Spread (SRnS)
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.4
0.6 0.7
ps
(rms)
1,2,3,5
1
Guaranteed by design and characterization, not 100% tested in production.
5
Applies to all differential outputs
Phase Jitter, PLL Mode
t
jphPCIeG2
2
See http://www.pcisi
g
.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Calculated from Intel-supplied Clock Jitter Tool
6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS 8 OCTOBER 18, 2016
9FGU0641 DATASHEET
Electrical Characteristics–REF
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
Clock Periods–Single-ended Outputs
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1,2
Clock period T
p
eriod
25 MHz output 40 ns 2
Rise/Fall Slew Rate t
rf1
Byte 3 = 1F, 20% to 80% of VDDREF 0.3 0.7 1.1 V/ns 1
Rise/Fall Slew Rate t
rf1
Byte 3 = 5F, 20% to 80% of VDDREF 0.5 1.0 1.6 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = 9F, 20% to 80% of VDDREF 0.77 1.3 1.9 V/ns 1
Rise/Fall Slew Rate t
rf1
Byte 3 = DF, 20% to 80% of VDDREF 0.84 1.4 2.0 V/ns 1
Duty Cycle d
t1X
V
T
= VDD/2 V 45 47.1 55 % 1,4
Duty Cycle Distortion d
tcd
V
T
= VDD/2 V, when driven by XIN/CLKIN_25 pin 0 2.00 4 % 1,5
Jitter, cycle to cycle t
j
c
y
c-c
y
c
V
T
= VDD/2 V 51.2 250 ps 1,4
Noise floor t
j
dBc1k
1kHz offset -126 -105 dBc 1,4
Noise floor t
j
dBc10k
10kHz offset to Nyquist -139 -110 dBc 1,4
Jitter, phase t
jphREF
12kHz to 5MHz 1.11 3
ps
(rms)
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
3
Default SMBus Value
4
When driven by a crystal.
5
X2 should be floating.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
0
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2
Notes
Measurement Window
UnitsSSC OFF
Center
Freq.
MHz
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
REF 25.000 39.79880 39.99880 40.00000 40.00120 40.20120 ns 1,2
Measurement Window
Units NotesSSC OFF
Center
Freq.
MHz
OCTOBER 18, 2016 9 6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
9FGU0641 DATASHEET
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Note: SMBus address is latched on SADR pin.
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
P1-P3P4-P6P7-P9P10-P12P13-P15

9FGU0641AKILF

Mfr. #:
Buy 9FGU0641AKILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 6-output 1.5 V PCIe Gen1-2-3 Clock Gen
Lifecycle:
New from this manufacturer.
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