PIN # PIN NAME PIN TYPE DESCRIPTION
1 vSS_EN_tri
LATCHED
IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
2 X1_25 IN Crystal input, Nominally 25.00MHz.
3 X2 OUT Crystal output.
4 VDDXTAL1.5 PWR Power supply for XTAL, nominal 1.5V
5 VDDREF1.5 PWR VDD for REF output. nominal 1.5V.
6 vSADR/REF1.5
LATCHED
I/O
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
7 NC N/A No Connection.
8 GNDDIG GND Ground pin for digital circuitry
9 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
10 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
11 VDDDIG1.5 PWR 1.5V digital power (dirty power)
12 VDDIO PWR Power supply for differential outputs
13 vOE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
14 DIF0 OUT Differential true clock output
15 DIF0# OUT Differential Complementary clock output
16 VDD1.5 PWR Power supply, nominally 1.5V
17 VDDIO PWR Power supply for differential outputs
18 DIF1 OUT Differential true clock output
19 DIF1# OUT Differential Complementary clock output
20 NC N/A No Connection.
21 vOE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
22 DIF2 OUT Differential true clock output
23 DIF2# OUT Differential Complementary clock output
24 vOE2# IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
25 NC N/A No Connection.
26 VDDA1.5 PWR 1.5V power for the PLL core.
27 VDDIO PWR Power supply for differential outputs
28 DIF3 OUT Differential true clock output
29 DIF3# OUT Differential Complementary clock output
30 vOE3# IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
31 VDD1.5 PWR Power supply, nominally 1.5V
32 VDDIO PWR Power supply for differential outputs
33 DIF4 OUT Differential true clock output
34 DIF4# OUT Differential Complementary clock output
35 vOE4# IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
36 DIF5 OUT Differential true clock output
37 DIF5# OUT Differential Complementary clock output
38 vOE5# IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
39 VDDIO PWR Power supply for differential outputs
40 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
41 ePAD GND Connect paddle to ground.
