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CBTU04082BS,518

P1-P3P4-P6P7-P9P10-P12P13-P15
CBTU04082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 13 July 2010 4 of 15
NXP Semiconductors
CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
6.2 Pin description
Table 2. Pin description
Symbol Pin Type Description
A0_P 2 I/O channel 0, port A differential signal input/output
A0_N 3 I/O
A1_P 6 I/O channel 1, port A differential signal input/output
A1_N 7 I/O
A2_P 11 I/O channel 2, port A differential signal input/output
A2_N 12 I/O
A3_P 15 I/O channel 3, port A differential signal input/output
A3_N 16 I/O
B0_P 38 I/O channel 0, port B differential signal input/output
B0_N 37 I/O
B1_P 36 I/O channel 1, port B differential signal input/output
B1_N 35 I/O
B2_P 29 I/O channel 2, port B differential signal input/output
B2_N 28 I/O
B3_P 27 I/O channel 3, port B differential signal input/output
B3_N 26 I/O
C0_P 34 I/O channel 0, port C differential signal input/output
C0_N 33 I/O
C1_P 32 I/O channel 1, port C differential signal input/output
C1_N 31 I/O
C2_P 25 I/O channel 2, port C differential signal input/output
C2_N 24 I/O
C3_P 23 I/O channel 3, port C differential signal input/output
C3_N 22 I/O
SEL 9 CMOS
single-ended input
operation mode select
SEL = 0: A → B
SEL = 1: A → C
V
DD
5, 8, 13, 18, 20,
30, 40, 42
power positive supply voltage, 1.8 V to 2.0 V (± 0.1 V)
GND 1, 4, 10, 14, 17,
19, 21, 39, 41,
center pad
power supply ground
CBTU04082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 13 July 2010 5 of 15
NXP Semiconductors
CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
7. Functional description
Refer to Figure 1 “Functional diagram of CBTU04082”.
7.1 Function selection
8. Limiting values
9. Static characteristics
[1] Typical values are at V
DD
= 1.8 V, T
amb
=25°C, and maximum loading.
[2] Input leakage current is ±50 μA if differential pairs are pulled to HIGH and LOW.
Table 3. Function selection
SEL Function
L An to Bn
H An to Cn
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage referenced to GND −0.5 +2.5 V
V
I
input voltage −0.5 V
DD
V
I
O
output current - 120 mA
P power dissipation - 0.5 W
T
stg
storage temperature −65 +150 °C
Table 5. Static characteristics
V
DD
= 1.8 V
±
10 %; T
amb
=
−
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
I
DD
supply current V
DD
= max.; V
I
=GNDorV
DD
--4mA
I
IH
HIGH-level input current V
DD
= max.; V
I
=V
DD
--±5
[2]
μA
I
IL
LOW-level input current V
DD
= max.; V
I
=GND - - ±5
[2]
μA
V
IH
HIGH-level input voltage guaranteed HIGH level 0.65V
DD
--V
V
IL
LOW-level input voltage guaranteed LOW level −0.5 - 0.15V
DD
V
V
IK
input clamping voltage V
DD
= max.; I
I
= −18 mA - −0.7 −1.2 V
CBTU04082 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 13 July 2010 6 of 15
NXP Semiconductors
CBTU04082
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
10. Dynamic characteristics
[1] Typical values are at V
DD
= 1.8 V; T
amb
=25°C, and maximum loading.
Table 6. Dynamic characteristics
V
DD
=1.8V
±
10 %; T
amb
=
−
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
α
ct
crosstalk attenuation f = 3 GHz - −23 - dB
f=100MHz - −58 - dB
α
iso(off)
off-state isolation f = 3 GHz - −23 - dB
f=100MHz - −58 - dB
DDIL differential insertion loss f = 3 GHz - −2- dB
B
−3dB
−3 dB bandwidth - 4.1 - GHz
t
PD
propagation delay from left-side port to
right-side port, or vice versa
-80-ps
Switching characteristics
t
PZH
OFF-state to HIGH propagation delay - - 8.0 ns
t
PZL
OFF-state to LOW propagation delay - - 8.0 ns
t
PHZ
HIGH to OFF-state propagation delay - - 8.0 ns
t
PLZ
LOW to OFF-state propagation delay - - 8.0 ns
t
sk(dif)
differential skew time intra-pair - - 10 ps
t
sk
skew time inter-pair - - 35 ps
Output 1 is for an output with internal conditions such that the output is LOW except when disabled
by the output control.
Output 2 is for an output with internal conditions such that the output is HIGH except when disabled
by the output control.
The outputs are measured one at a time with one transition per measurement.
Fig 3. Voltage waveforms for enable and disable times
002aae65
4
V
DD
t
PLZ
0.5V
DD
0.5V
DD
SEL
output 1
0.5V
DD
t
PZL
V
OL
0 V
V
OL
+ 0.15 V
V
OH
0.5V
DD
V
OH
− 0.15 V
output 2
t
PZH
t
PHZ
V
OL
V
OH
P1-P3P4-P6P7-P9P10-P12P13-P15

CBTU04082BS,518

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