OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MAX2395ETI+T

P1-P3P4-P6P7-P9P10-P12P13-P13
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
4 _______________________________________________________________________________________
PARAMETER CONDITIONS MIN TYP MAX UNITS
ON-CHIP VCO
Phase Noise
At 3MHz offset, measured at the center of the RF band
(Note 6)
-130 -128 dBc/Hz
Supply Pushing
Supply stepped from +2.7V to +3.3V, with on-chip
voltage regulator
±0.15 MHz/V
RF VCO Pulling When switching from IDLE mode to active Tx mode ±0.1 MHz
P-P
3-WIRE SERIAL BUS INTERFACE
Data to Clock Setup, t
CS
Figure 1 (Note 6) 20 ns
Data to Clock Hold Time, t
CH
Figure 1 (Note 6) 10 ns
Clock Pulse-Width High, t
CWH
Figure 1 (Note 6) 20 ns
Clock Pulse-Width Low, t
CWL
Figure 1 (Note 6) 20 ns
Clock to Load Enable/Setup
Time, t
ES
Figure 1 (Note 6) 20 ns
Clock Frequency (Note 6) 20 MHz
Note 1: The following parameters are characterized using the register settings below.
Note 2: Guaranteed at T
A
= +25°C and T
A
= +85°C by production test, and guaranteed by design and characterization at T
A
= -40°C.
Note 3: V
DH
is the high voltage applied to the shutdown pin.
Note 4: Output power, linearity, noise power, and LO leakage specifications are met over this frequency range.
Note 5: Specifications valid for all output power levels, unless limited by thermal noise at lower output power levels.
Note 6: Guaranteed by design and characterization.
Note 7: Tested at 1MHz and 2MHz in the passband.
Table 1. Characterization Register Settings
AC ELECTRICAL CHARACTERISTICS (continued)
MAX2395 EV kit, V
CC
= +2.7V to +3.3V, R
BIAS
= 12kΩ,V
VGC
adjusted to obtain maximum rated output power, and T
A
= -40°C to
+85°C. I/Q inputs driven differentially with low- impedance source based on 3GPP UpLink reference measurement channel
(12.2kbps), envelope level 1V
P-P
. Typical values are at V
CC
= +2.85V and T
A
= +25°C, unless otherwise noted. See Tables 1 and 3 for
register settings.) (Note 2)
REGISTER SETTINGS ADDRESS FUNCTION
RFR
4050 hex
(80 dec for ÷R)
0000
b
Reference-divider register
OPCTRL 3B7D hex 0100
b
Operational control settings
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
_______________________________________________________________________________________
5
Typical Operating Characteristics
(V
CC
= +2.85V, f
RF
= 1950MHz, MPL = 1, and T
A
= +25°C, unless otherwise noted.)
EVM vs. P
OUT
MAX2395 toc01
P
OUT
(dBm)
EVM (%
RMS
)
2-2-6-10-14-18-22-26
5
6
7
8
9
10
4
-30 6
T
A
= +25
°
C
T
A
= +85
°
C
T
A
= -40
°
C
P
OUT
ACPR1 vs. V
VGC
MAX2395 toc02
V
VGC
(V)
P
OUT
(dBm), ACPR (dBc)
2.12.01.6 1.7 1.8 1.9
-50
-40
-30
-20
-10
0
10
20
-60
1.5 2.2
T
A
= +85
°
C
T
A
= +25
°
C
T
A
= -40
°
C
OUTPUT SPECTRUM vs. FREQUENCY
MAX2395 toc03
FREQUENCY (GHz)
OUTPUT SPECTRUM (dBm)
2.82.62.2 2.41.4 1.6 1.8 2.01.2
-80
-70
-60
-50
-40
-30
-20
-10
0
10
-90
1.0 3.0
WANTED SIGNAL, 0dB
RF LO-2IF,
-32dB
RF LO-3IF,
-35dB
RF LO, -42dB
RF IMAGE, 15dB
OUTPUT NOISE DENSITY vs. V
VGC
MAX2395 toc04
V
VGC
(V)
OUTPUT POWER NOISE DENSITY (dBm/Hz)
2.0
1.81.6
1.4
1.21.0
-150
-152
-146
-148
-142
-144
-138
-140
-132
-134
-136
-130
-154
0.8 2.2
f
RF
= 1922.4MHz
f = 1880MHz
T
A
= +25
°
C
T
A
= +85
°
C
f = 2112.4MHz
T
A
= -40
°
C
I
CC
vs. V
VGC
MAX2395 toc05
V
VGC
(V)
I
CC
(mA)
1.4 1.6
0.6
0.8 1.0
1.2
30
40
60
50
70
80
90
100
110
20
0.4 1.8
2.0
2.2
V
CC
= 2.7V TO 3.3V,
INPUT APPLIED
T
A
= +85
°
C
T
A
= -40
°
C
T
A
= +25
°
C
BASEBAND FILTER REPSONSE
MAX2395 toc06
FREQUENCY (MHz)
FILTER RESPONSE (dB)
18161412108642
-50
-40
-30
-20
-10
0
10
-60
020
CARRIER AND SIDEBAND SUPPRESSION
vs. P
OUT
MAX2395 toc07
P
OUT
(dBm)
CARRIER AND SIDEBAND SUPPRESSION (dBc)
-4-14-24-34-44-54-64
10
20
30
40
50
60
0
-74 6
SIDEBAND
CARRIER
VGC SLOPE LINEARITY vs. P
OUT
MAX2395 toc08
P
OUT
(dBm)
SLOPE (dB/V)
-4-14-34 -24-54 -44-64-74 6
35
40
45
50
55
60
65
70
30
T
A
= -40
°
C
T
A
= +25
°
C
T
A
= +85
°
C
FREQUENCY SETTLING TIME
MAX2395 toc09
TIME (µs)
FREQUENCY (kHz)
800700600500400300200100
-20
-15
-10
-5
0
5
10
-25
0900
FROM IDLE
FROM 1920MHz
TO 1980MHz
FROM SHDN
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
6 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 N.C. Connect to RF GND on PCB
2 POUT
Transmitter Output. This is an open-collector output and requires a pullup inductor to the supply
voltage. This pullup inductor can be part of the output matching network and can be connected
directly to the battery.
3V
CC
_PA
Supply for the PA Driver. This pin must be bypassed with a capacitor to system ground as close to
the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see
the Typical Operating Circuit).
4
BIAS_SET
Bias-Setting Pin. The DC voltage at this pin is a bandgap voltage. For nominal bias, connect a 12kΩ
resistor to ground. The value of this resistor can be adjusted to alter current consumption, linearity,
and noise performance of the RF output.
5 VGC
Gain-Control Pin. Analog input pin controls both the IF VGA and RF VGA gain. When not driven, the
voltage on this pin is typically +1.5V. An RC filter on this pin must be used to filter out DAC noise or
the PDM clock.
6V
CC
_IF
Supply for IF Section. Bypass to system ground with a capacitor as close to the pin as possible. Do
not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating
Circuit).
7V
CC
_BB
Supply for Baseband Section. Bypass to system ground with a capacitor as close to the pin as
possible. Do not share the ground vias for the bypass capacitor with any other branch (see the
Typical Operating Circuit).
8 IDLE
Idle CMOS Digital Input. Drive LOW to place the device in WCDMA compressed mode (VCO and PLL
are ON; all others are OFF). A small RC lowpass filter can be used to minimize the effect of external
digital noise.
9 SHDN
Shutdown CMOS Digital Input. Drive LOW to place the device in shutdown (everything OFF except
serial interface and registers, which retain their values). A small RC lowpass filter can be used to
minimize the effect of external digital noise. A logic-low on the SHDN pin overrides the serial bus
SHDN bit status.
10, 11 I+, I- Differential I-Channel Baseband Inputs to the Baseband Filter
12, 13 Q+, Q- Differential Q-Channel Baseband Inputs to the Baseband Filter
N.C. Leave Open
15 LD Lock CMOS Output. This pin is an open-drain output. Output HIGH indicates the RF PLL is locked.
16 REF
Reference Frequency Input. This pin is internally biased to approximately +1.0V and must be AC-
coupled to the reference source. This is a high-impedance port and can be externally terminated to
the desired impedance.
17 V
CC
_PLL Supply for PLL. Bypass with a capacitor to GND (see the Typical Operating Circuit).
18 V
CC
_CP
Supply for Synthesizer Charge Pump. Bypass with a capacitor to GND (see the Typical Operating
Circuit).
19 RFCP
RF Charge-Pump Output. Connect the RF PLL’s loop filter between RFCP and system ground. Keep
the line from this pin to the tank tune input as short as possible to prevent spurious pickup. Connect
the loop filter as close to the tune input as possible.
P1-P3P4-P6P7-P9P10-P12P13-P13

MAX2395ETI+T

Mfr. #:
Buy MAX2395ETI+T
Manufacturer:
Maxim Integrated
Description:
Modulator / Demodulator WCDMA Quasi-Direct Modulator w/VGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet