MAX6604AAHA+ Datasheet MAX6604AAHA+, MAX6604ATA+T, MAX6604ATA+TW | P7-P9

EVENT-Output Functionality

The EVENT output indicates conditions such as the

temperature crossing a predefined boundary. It oper-

ates in one of the three modes: interrupt mode, com-

parator mode, and critical-temperature-only mode.

Figure 3 shows an example of the measured tempera-

ture vs. time, with the corresponding behavior of the

EVENT output in each of these modes. See the

EVENT

Operation Modes

section for descriptions of the two

modes. The EVENT modes are selected using the con-

figuration register.

Event-output polarity can be set to active high or active

low through the configuration register (bit 1). The

EVENT output can also be disabled so that EVENT is

always high impedance (bit 3). Upon device power-up,

the default condition for the EVENT output is high

impedance. Writing a 1 to bit 3 of the configuration reg-

ister enables the EVENT output.

EVENT Thresholds

Alarm Window Trip

The MAX6604 provides a comparison window with an

upper-temperature trip point and a lower-temperature

trip point, programmed through the alarm-upper-

boundary register and the alarm-lower-boundary regis-

ter, respectively. When enabled, the EVENT output

triggers whenever entering or exiting (crossing above

or below) the alarm window (Figure 3).

Critical Trip

The critical temperature setting is programmed in the

critical temperature register. When the temperature

reaches the critical temperature value in this register

(and EVENT is enabled), the EVENT output asserts and

cannot be deasserted until the temperature drops

below the critical temperature threshold.

EVENT Operation Modes

Comparator Mode

In comparator mode, the EVENT output behaves like a

window-comparator output that asserts when the tem-

perature is outside the window. Reads/writes on the

MAX6604’s registers do not affect the EVENT output in

comparator mode. The EVENT signal remains asserted

until the temperature goes inside the alarm window or

the window thresholds are reprogrammed so that the

current temperature is within the alarm window.

Interrupt Mode

In interrupt mode, EVENT asserts whenever the temper-

ature crosses an alarm window threshold. After such an

event occurs, writing a 1 to the clear event bit in the con-

figuration register deasserts the EVENT output until the

next trigger condition occurs. The trip threshold value in

MAX6604

Precision Temperature Monitor for

DDR Memory Modules

_______________________________________________________________________________________ 7

S/W CLEARS EVENT

EVENT# IN CRITICAL-TEMPERATURE-ONLY MODE

EVENT# IN COMPARATOR MODE

EVENT# IN INTERRUPT

ALARM WINDOW

CRITICAL

TEMP

TIME

Figure 3. EVENT Behavior in Interrupt, Comparator, and Critical-Temperature-Only Modes

MAX6604

the critical temperature register is likely to be higher than

that of the alarm-upper-boundary register. As a result,

when the temperature is above the critical temperature,

it is likely that it is above the alarm-upper-boundary as

well. In interrupt mode, EVENT asserts when the temper-

ature crosses the alarm upper boundary.

If the EVENT output is cleared and the temperature

continues to increase until it crosses the critical temper-

ature threshold, EVENT asserts again. Because the

temperature is greater than the critical temperature

threshold, a clear event command does not clear the

EVENT output. Once the temperature drops below the

critical temperature, EVENT deasserts immediately.

If the EVENT output is not cleared before the tempera-

ture goes above the critical temperature threshold,

EVENT remains asserted. Attempting a clear event

command has no effect until the temperature drops

below the critical temperature, at which point EVENT

deasserts immediately because of the earlier clear

event command. If no clear event command is attempt-

ed, EVENT remains asserted after the temperature

drops below the critical temperature. At this point, a

clear event command deasserts EVENT.

Detailed Register Descriptions

Capability Register (Read Only)

[Address = 00h, POR = 0017h]

This register indicates the capabilities of the thermal

sensor, including accuracy, temperature range, and

resolution. See Table 3 for register details.

Configuration Register (Read/Write)

[Address = 01h, POR = 0000h]

This register controls the various features of EVENT

functionality, and controls the bit for thermal-sensor

shutdown mode. See Table 4 for register details.

Hysteresis

When enabled, hysteresis is applied to temperature varia-

tions around trigger points. For example, consider the

behavior of the alarm window bit (bit 14 of the tempera-

ture register) when the hysteresis is set to 3°C. As the

temperature rises, bit 14 is set to 1 (temperature is above

the alarm window) when the temperature register con-

tains a value that is greater than the value in the alarm

temperature upper boundary register. If the temperature

decreases, bit 14 remains set until the measured temper-

ature is less than or equal to the value in the alarm tem-

perature upper boundary register minus 3°C.

Precision Temperature Monitor for

DDR Memory Modules

8 _______________________________________________________________________________________

Table 3. Capability Register (Read Only)

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RFU

TRES1

TRES0

Wider range

Higher

precision

Has alarm and

critical trips

BIT DEFINITION (DESCRIPTIONS IN BOLD TYPE APPLY TO THE MAX6604)

Basic capability

1: Has alarm and critical trips capability

Accuracy

0 = Default accuracy ±2°C over the active and ±3°C monitor ranges

1 = High accuracy ±1°C over the active and ±2°C monitor ranges

Wider range

0 = Values lower than 0°C are clamped and represented as binary value 0

1 = Can read temperature below 0°C and set sign bit accordingly

4:3

Temperature resolution

00 = 0.5°C LSB

01 = 0.25°C LSB

10 = 0.125°C LSB

11 = 0.0625°C LSB

15:5 0: Reserved for future use (RFU). Must be zero.

MAX6604

Precision Temperature Monitor for

DDR Memory Modules

_______________________________________________________________________________________ 9

Table 4. Configuration Register (Read/Write)

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RFU

Hysteresis

Shutdown mode

Critical trip

lock bit

Alarm window

lock bit

Clear EVENT

EVENT output

status

EVENT output

control

Critical EVENT

only

EVENT polarity

EVENT mode

BIT DEFINITION (DESCRIPTIONS IN BOLD TYPE ARE THE DEFAULT VALUES)

EVENT mode

0 = Comparator output mode (default)

1 = Interrupt mode

When either of the lock bits is set, this bit cannot be altered until unlocked.

EVENT polarity

0 = Active low (default)

1 = Active high

When either of the lock bits is set, this bit cannot be altered until unlocked.

Critical EVENT only

0 = EVENT output on alarm or critical temperature mode (default)

1 = EVENT only if temperature is above the value in the critical temp register

When the alarm window lock bit is set, this bit cannot be altered until unlocked.

EVENT output control

0 = EVENT output disabled (default) [Disabled means EVENT remains in an inactive voltage level]

1 = EVENT output enabled

When either of the lock bits is set, this bit cannot be altered until unlocked.

EVENT output status (read only)

0 = EVENT output condition is not being asserted by this device

1 = EVENT output is being asserted by this device due to alarm window or critical trip condition

The actual conditions causing an EVENT output can be determined from the temperature register. Interrupt mode can be

cleared by writing to the clear EVENT bit. Writing to this bit has no effect; this bit is not affected by the polarity setting.

Clear EVENT (write only)

0 = No effect

1 = Clears active event in interrupt mode. Writing to this register has no effect in comparator mode

When read, this bit always returns to zero.

Alarm window lock bit

0 = Alarm trips are not locked and can be altered (default)

1 = Alarm trip register settings cannot be altered

This bit is initially cleared. When set, this bit returns a 1 and remains locked until cleared by the internal power-on reset.

Lock bits and other configuration register bits are updated during the same write; double writes are not necessary.

Critical trip lock bit

0 = Critical trip is not locked and can be altered (default)

1 = Critical trip register settings cannot be altered

This bit is initially cleared. When set, this bit returns a 1 and remains locked until cleared by the internal power-on reset.

Lock bits and other configuration register bits are updated during the same write; double writes are not necessary.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MAX6604AAHA+

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Board Mount Temperature Sensors Precision Temperature Monitor for DDR Memory Modules

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MAX6604AAHA+

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