LPC122X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 26 August 2011 37 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Conditions: V
DD(3V3)
= 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(3) System oscillator enabled with external clock input; IRC and system PLL disabled.
Fig 10. Sleep mode: Typical supply current I
DD
versus supply voltage V
DD(3V3)
for
different system clock frequencies
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
Fig 11. Deep-sleep mode: Typical supply current I
DD
versus temperature for different
supply voltages V
DD(3V3)
V
DD(3V3)
(V)
3.0 3.63.43.2
002aag188
2
3
1
4
5
I
DD
(mA)
0
33 MHz
(2)
24 MHz
(2)
12 MHz
(1)
1 MHz
(3)
4 MHz
(3)
002aag190
20
40
30
50
I
DD
(μA)
10
temperature (°C)
-40 853510 60-15
V
DD(3V3)
= 3.6 V
3.3 V
3.0 V
