AD7821
REV. B
–9–
SIGNAL-TO-NOISE RATIO AND DISTORTION
The dynamic performance of the AD7821 is evaluated by apply-
ing a very low distortion sine wave signal to the analog input
(V
IN
) which is then sampled at a 512 kHz sampling rate. A Fast
Fourier Transform (FFT) plot is then generated from which
Signal-to-Noise Ratio (SNR) and harmonic distortion data are
obtained.
Figure 8 shows a 2048 point FFT plot of the AD7821 with an
input signal of 100.25 kHz. The SNR is 49.1 dB. It should be
noted that the harmonics are taken into account when calculat-
ing the SNR. The theoretical relationship between SNR and
resolution (N) is expressed by the following equation:
SNR N dB=+
()
602 176..
(1)
Figure 8. FFT Plot
EFFECTIVE NUMBER OF BITS
By working backwards from Equation (1) it is possible to get a
measure of ADC performance expressed in effective number of
bits (N). A plot of the effective number of bits versus input
frequency is given in the Typical Performance Characteristics
section. The effective number of bits typically falls between 7.7
and 7.9, corresponding to SNR figures of 48.1 dB and 49.7 dB.
INTERMODULATION DISTORTION
For intermodulation distortion (IMD), an FFT plot consisting
of very low distortion sine waves at two frequencies is generated
by sampling an analog input applied to the ADC. Figure 9
shows a 2048 point plot for IMD.
Figure 9. FFT Plot for IMD
HISTOGRAM PLOT
When a sine wave of specified frequency is applied to the V
IN
input
of the AD7821 and several thousand samples are taken, it is
possible to plot a histogram showing the frequency of occurrence
of each of the 256 ADC codes. A perfect ADC produces a
probability density function described by the equation:
P(V ) =
1
π( A
2
V
2
)
1/ 2
where A is the peak amplitude of the sine wave and P(V) is the
probability of occurrence at a voltage V.
If a particular step is wider than the ideal 1 LSB width, then the
code associated with that step will accumulate more counts than
for the code for an ideal step. Likewise, a step narrower than the
ideal width will have fewer counts. Missing codes are easily seen
because a missing code means zero counts for a particular code.
The absence of large spikes in the plot indicates small differ-
ential nonlinearity.
Figure 10 shows a histogram plot for the AD7821, which corre-
sponds very well with the ideal shape. The plot indicates very
small differential nonlinearity and no missing codes for an input
frequency of 100.25 kHz.
Figure 10. Histogram Plot
In digital signal processing applications, where the AD7821 is
used to sample ac signals, it is essential that the signal sampling
occurs at exactly equal intervals. This minimizes errors due to
sampling uncertainty or jitter. A precise timer or clock source,
to start the ADC conversion process, is the best method of gen-
erating equidistant sampling intervals.
The two modes of operation given in the data sheet are suitable
for DSP applications because the sampling instant of the
AD7821 is well defined. V
IN
is sampled on the falling edge of
WR or RD in the WR-RD or RD modes, respectively.
DIGITAL INTERFACE
The AD7821 has two basic interface modes which are determined
by the status of the MODE pin. When this pin is low, the
converter is in the RD mode, with this pin high, the AD7821 is
set up for the WR-RD mode.
The RD mode is designed for microprocessors that can be driven
into a WAIT state. A READ operation (i.e., CS and RD are taken
low) starts a conversion and data is read when the conversion is
complete. The WR-RD mode does not require microprocessor
WAIT states. A WRITE operation (i.e., CS and WR are taken
low) initiates a conversion, and a READ operation reads the
result when the conversion is complete.
AD7821
REV. B
–10–
RD Mode (MODE = 0)
The timing diagram for the RD mode is shown in Figure 11.
This mode is intended for use with microprocessors that have a
WAIT state facility, whereby a READ instruction cycle can be
extended to accommodate slow memory devices. A conversion
is started by taking CS and RD low (READ operation). Both
CS and RD are then kept low until output data appears.
Figure 11. RD Mode
In this mode, Pin 6 of the AD7821 is configured as a status out-
put, RDY. This RDY output can be used to drive the processor
READY or WAIT input. It is an open-drain output (no inter-
nal-pull-up device) which goes low after the falling edge of CS
and goes high impedance at the end of conversion. An INT line is
also provided which goes low when a conversion is complete.
INT returns high on the rising edge of CS or RD.
WR-RD Mode (MODE = 1)
In the WR-RD mode, Pin 6 is configured as a WRITE (WR)
input for the AD7821. With CS low, conversion is initiated on
the falling edge of WR. Two options exist for reading data from
the converter.
In the first of these options the processor waits for the INT status
line to go low before reading the data (see Figure 12a).
INT typically goes low within 380 ns after the rising edge of WR.
It indicates that conversion is complete and that the data result is
in the output latch. With CS low, the data outputs (DB0–DB7)
are activated when RD goes low. INT is reset by the rising edge
of RD or CS.
Figure 12a. WR-RD Mode (t
RD
> t
INTL
)
The alternative option can be used to shorten the conversion time.
This is a method for bypassing the internal time-out circuit. The
INT line is ignored and RD can be brought low 250 ns after the
rising edge of WR. In this case RD going low transfers the data
result into the output latch and activates the data output
(DB0–DB7). INT is driven low on the falling edge of RD and is
reset on the rising edge of RD or CS. The timing for this interface
is shown in Figure 12b.
Figure 12b. WR-RD Mode (t
RD
< t
INTL
)
The AD7821 can also be used in standalone operation in the
WR-RD mode. CS and RD are tied low, and a conversion is initi-
ated by bringing WR low. Output data is valid 530 ns (t
INTL
+ t
ID
)
after the rising edge of WR. The timing diagram for this mode is
shown in Figure 13.
Figure 13. WR-RD Mode Stand-Alone Operation,
CS
=
RD
= 0
AD7821
REV. B
–11–
MICROPROCESSOR INTERFACING
The AD7821 is designed for easy interfacing to microprocessors
as a memory mapped peripheral or an I/O device. This reduces
to a minimum the amount of external logic required for
interfacing.
AD7821 – 68008 INTERFACE
Figure 14 shows an AD7821 interface to the 68008 micropro-
cessor. The ADC is configured for the RD interface mode. This
means that one read instruction starts a conversion and reads
the result when the conversion is completed. The read cycle is
stretched out over the entire conversion period by taking the
INT line back to the DTACK input of the 68008. Starting a
conversion and reading the relevant data consists of a <MOVE B
Dn, addr> instruction, where addr is the decoded ADC address and
Dn is the data register into which the result is placed.
Figure 14. AD7821 to 68008 Interface
AD7821 – 8088 INTERFACE
A typical interface to the 8088 is shown in Figure 15. The AD7821
is configured for the RD interface mode. One read instruction
starts a conversion and reads the result. The read cycle is stretched
out over the entire conversion period by taking the RDY line back
to the READY input of the 8088. Starting a conversion and
reading the result consists of a <MOV AX, (addr)> instruction,
where addr is the decoded ADC address and AX is the 8088 data
register into which the conversion result is placed.
Figure 15. AD7821 to 8088 Interface
AD7821 – TMS32010 INTERFACE
A typical interface to the TMS32010 is shown in Figure 16. The
AD7821 is mapped at a port address and the interface is designed
for the maximum TMS32010 clock frequency of 20 MHz. In this
case, the AD7821 is configured in the WR-RD interface mode.
This means that a write instruction starts a conversion and a read
instruction reads the result when the conversion is completed. A
precise timer or clock source is used to start a conversion in
applications requiring equidistant sampling intervals. The
scheme used, whereby the AD7821 generates an interrupt to
the TMS32010, is limited in that it does not allow the AD7821
to be sampled at its maximum rate. This is because the time
between samples has to be long enough to allow the TMS32010
to service its interrupt and read data from the AD7821.
Constant interruption of the TMS32010 by the AD7821, every time
the ADC completes a conversion, is not a very efficient use of
the processor time. To overcome these problems, some buffer
memory or FIFO could be placed between the AD7821 and the
TMS32010. The INT line of the AD7821 could be used to
trigger a pulse which drives its CS and RD lines and places the
AD7821 data into a FIFO or buffer memory. The microproces-
sor can then read a batch of data from the FIFO or buffer memory
at some convenient time. Reading data from the AD7821, after an
INT has been received, consists of a <IN A, PA> instruction
(PA is the decoded ADC address).
Figure 16. AD7821 to TMS32010 Interface
AD7821 – 8051 INTERFACE
Figure 17 shows the AD7821 interface to the 8051 microcom-
puter. The AD7821 is configured in the WR-RD interface mode
and is connected to the 8051 ports. The processor starts conver-
sion and then polls INT, until it goes low, before reading the
conversion result. Data is read from the AD7821 by using the
<MOV A, 90H> instruction (90H is the address for Port 1).
Figure 17. AD7821 to 8051 Interface

AD7821KRZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Hi Spd uP-Compatible CMOS 8B Sampling
Lifecycle:
New from this manufacturer.
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