MK3732-10
VCXO AND MULTIPLIER VCXO AND MULTIPLIER
IDT™
VCXO AND MULTIPLIER 3
MK3732-10 REV D 122109
Pin Descriptions
Pin Descriptions
The MK3732-10 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01µF should be connected
between VDD and GND on pins 2 and 5 and pins 3 and 6,
as close to the MK3732-10 as possible. For optimum device
performance, the decoupling capacitors should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs (CLK, pin
5) and the loads are over 1 inch, series termination should
be used. To series terminate a 50Ω trace (a commonly used
trace impedance) place a 33Ω resistor in series with the
clock line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20Ω.
Quartz Crystal
The MK3732-10 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To assure
the best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the following section must be
followed.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
MK3732-10 incorporates on-chip variable load capacitors
that “pull” (change) the frequency of the crystal. The crystal
specified for use with the MK3732-10 is designed to have
zero frequency error when the total of on-chip + stray
capacitance is 14pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
° C±20 ppm
Temperature Stability ±30 ppm
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 XI XI Crystal connection. Connect to a pullable of 16 to 28 MHz cyrstal.
2 - 3 VDD Power Connect to +3.3 V.
4 VIN Input Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency.
5 - 6 GND Power Connect to ground.
7 S3 Input Select input #3. Selects outputs per table above. Internal pull-up resistor.
8 S2 Input Select input #2. Selects outputs per table above. Internal pull-up resistor.
9PDCLK3
Input Power down for CLK3.
10 S0 Input Select input #0. Selects outputs per table above. Internal pull-up resistor.
11 CLK3 Output PLL output clock that is either a multiple of the input or an audio clock. See table
above.
12 REF Output Buffered VCXO reference clock output. Matches crystal frequency.
13 REF/2 Output Reference clock output divided by two.
14 S1 Input Select input #1. Selects outputs per table above. Internal pull-up resistor.
15 OE Input Output enable. Tri-states outputs when low. Internal pull-up resistor.
16 X2 XO Crystal connection. Connect to a pullable 16 to 28 MHz crystal.
