© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 4
1 Publication Order Number:
NB3N551/D
NB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed
for clock distribution in mind. The NB3N551 specifically guarantees
low output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin three−states the outputs when low.
Features
• Input/Output Clock Frequency up to 180 MHz
• Low Skew Outputs (50 ps typical)
• RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
• Output goes to Three−State Mode via OE
• Operating Range: V
DD
= 3.0 V to 5.5 V
• Ideal for Networking Clocks
• Packaged in 8−pin SOIC
• Industrial Temperature Range
• These are Pb−Free Devices
Figure 1. Block Diagram
CLK
Q1
Q2
Q3
Q4
OE
Device Package Shipping
†
ORDERING INFORMATION
NB3N551DG SOIC−8
(Pb−Free)
98 Units/Rail
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
http://onsemi.com
1
8
3N551 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
3N551
ALYW
G
1
8
NB3N551DR2G SOIC−8
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Q4
GND
V
DD
OE
I
CLK
Q1
Q2
Q3
PIN CONNECTIONS
1
DFN8
MN SUFFIX
CASE 506AA
6K = Specific Device Code
M = Date Code
G = Pb−Free Package
6K MG
G
14
NB3N551MNR4G DFN−8
(Pb−Free)
1000/Tape & Reel
(Note: Microdot may be in either location)
1
2
3
4
8
7
6
5
*For additional marking information, refer to
Application Note AND8002/D.