NB3N551MNR4G

© Semiconductor Components Industries, LLC, 2012
July, 2012 Rev. 4
1 Publication Order Number:
NB3N551/D
NB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1to 4 clock fanout buffer, designed
for clock distribution in mind. The NB3N551 specifically guarantees
low outputtooutput skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin threestates the outputs when low.
Features
Input/Output Clock Frequency up to 180 MHz
Low Skew Outputs (50 ps typical)
RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
Output goes to ThreeState Mode via OE
Operating Range: V
DD
= 3.0 V to 5.5 V
Ideal for Networking Clocks
Packaged in 8pin SOIC
Industrial Temperature Range
These are PbFree Devices
Figure 1. Block Diagram
CLK
Q1
Q2
Q3
Q4
OE
Device Package Shipping
ORDERING INFORMATION
NB3N551DG SOIC8
(PbFree)
98 Units/Rail
SOIC8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
http://onsemi.com
1
8
3N551 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
3N551
ALYW
G
1
8
NB3N551DR2G SOIC8
(PbFree)
2500/Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Q4
GND
V
DD
OE
I
CLK
Q1
Q2
Q3
PIN CONNECTIONS
1
DFN8
MN SUFFIX
CASE 506AA
6K = Specific Device Code
M = Date Code
G = PbFree Package
6K MG
G
14
NB3N551MNR4G DFN8
(PbFree)
1000/Tape & Reel
(Note: Microdot may be in either location)
1
2
3
4
8
7
6
5
*For additional marking information, refer to
Application Note AND8002/D.
NB3N551
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2
Table 1. OE, OUTPUT ENABLE FUNCTION
OE Function
0 Disable
1 Enable
Table 2. PIN DESCRIPTION
Pin # Name Type Description
1 I
CLK
(LV)CMOS/(LV)TTL Input
Clock Input. Internal pull-up resistor.
2 Q1 (LV)CMOS/(LV)TTL Output
Clock Output 1
3 Q2 (LV)CMOS/(LV)TTL Output
Clock Output 2
4 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3
5 Q4 (LV)CMOS/(LV)TTL Output Clock Output 4
6 GND Power Negative supply voltage; Connect to ground, 0 V
7 V
DD
Power Positive supply voltage (3.0 V to 5.5 V)
8 OE (LV)CMOS/(LV)TTL Input Output Enable for the clock outputs. Outputs are enabled when HIGH or when left
open; OE pin has internal pullup resistor. Threestates outputs when LOW.
EP Thermal Exposed Pad (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave uncon-
nected, floating open.
NB3N551
http://onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
V
DD
Positive Power Supply GND = 0 V 7.0 V
V
I
/V
O
Input/Output Voltage t 1.5 ns GND–1.5 V
I
/V
O
V
DD
+1.5 V
T
A
Operating Temperature Range, Industrial 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
SOIC8 190
130
°C/W
°C/W
q
JC
Thermal Resistance (JunctiontoCase) (Note 1) SOIC8 41 to 44 °C/W
q
JA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
q
JC
Thermal Resistance (JunctiontoCase) (Note 1) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
Table 4. ATTRIBUTES
Characteristic Value
ESD Protection Human Body Model
Machine Model
> 4 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL94 code V0 @ 0.125 in
Transistor Count 531 Devices
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.

NB3N551MNR4G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:4 CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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