LT3667
11
3667fb
For more information www.linear.com/LT3667
PIN FUNCTIONS
(MSOP/QFN)
SW (Pin 1/Pin 24): The SW pin is the output of the internal
power switch. Connect this pin to the inductor, the catch
diode and the boost capacitor.
BOOST (Pin 2/Pin 1): This pin is used to provide a drive
voltage, higher than the input voltage, to the internal bipolar
NPN power switch of the switching regulator. Connect
a capacitor (typically 0.22μF) between BOOST and SW.
SYNC (Pin 2, QFN Only): This is the external clock syn
-
chronization input
.
Ground this pin for low ripple Burst
Mode operation at low output loads. Tie to a clock source
for synchronization. Refer to Synchronization section in
Applications Information for more details.
EN (Pin 3/Pin 3): The EN pin is used to put the LT3667 in
shutdown mode. Tie to ground to shut down the LT3667.
Tie to 1V or more for normal operation. If the EN pin is to
be pulled below ground, use a series resistor to limit the
pin current to 1mA.
RT (Pin 4/Pin 4): Oscillator Resistor Input. Connect a resis
-
tor from this pin to ground to set the switching frequency.
BD
(Pin 5, QFN Only): This pin connects to the anode of
the internal
boost diode. This pin also supplies current to
the LT3667’s internal regulator when BD is above 3.2V.
OUT
3 (Pin 6/Pin 7), OUT2 (Pin 10/Pin 14): These are the
outputs of the two LDOs. Stability requirements demand
a minimum 2.2μF ceramic output capacitor to prevent
oscillations.
FB3 (Pin 7/Pin 8), FB2 (Pin 9/Pin 13): The two LDOs of
the LT3667 regulate the FB2 and FB3 pins to 0.8V. Connect
the feedback resistor divider taps to these pins.
FB1 (Pin 8/Pin 10): The switching regulator of the LT3667
regulates the FB1 pin to 1.2V. Connect the feedback resis
-
tor divider tap to this pin.
PG
1
(Pin 9, QFN Only): The PG1 pin is the open-drain
output of an internal window comparator. PG1 remains
low until the FB1 pin is within ±10% of its final regulation
voltage. PG1 output is valid when V
IN1
or V
IN2
are above
the minimum input voltage and EN is high.
IN2 (Pin 11/Pin 15), IN3/BD (Pin 5, MSOP), IN3 (Pin 6,
QFN): These pins are the inputs of the two LDOs. IN3/BD
also connects to the anode of the internal boost diode and
also supplies current to the LT3667’s internal regulator
when IN3/BD is above 3.2V
.
PG2 (Pin 11, QFN Only): The PG2 pin is the open-drain
output of an internal window comparator. PG2 remains
low until the FB2 pin is within ±10% of its final regulation
voltage. PG2 output is valid when V
IN1
or V
IN2
are above
the minimum input voltage and EN is high.
EN2/ILIM2 (Pin 12/Pin 16), EN3/ILIM3 (Pin 13/Pin 17):
Precision current limit programming pins. They connect
to collectors of current mirror PNPs which are 1/799th
the size of the output power PNPs of the two LDOs. These
pins are also the inputs to the current limit amplifiers.
Current limit thresholds are set by connecting resistors
between the EN2/ILIM2 pin and GND and between the
EN3/ILIM3 pin and GND. Stability requirements demand
47nF capacitors in parallel to these resistors. For detailed
information on how to set the pin resistor values, see the
Operation section. If any of these pins is not used, tie it to
GND. To disable an LDO, pull its EN/ILIM pin above 1.2V.
PG3 (Pin 12, QFN Only): The PG3 pin is the open-drain
output of an internal window comparator. PG3 remains
low until the FB3 pin is within ±10% of its final regulation
voltage. PG3 output is valid when V
IN1
or V
IN2
are above
the minimum input voltage and EN is high.
PG (Pin 14/Pin 18): The PG pin is the open-drain output
of an internal window comparator. PG remains low until
the FB1, FB2, and FB3 pin are within ±10% of their final
regulation voltages. PG output is valid when V
IN1
or V
IN2
are above the minimum input voltage and EN is high.
