LT3667HUDD#PBF Datasheet LT3667IMSE#PBF, LT3667IUDD#PBF, LT3667HUDD#PBF | P19-P21

LT3667

3667fb

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APPLICATIONS INFORMATION

Figure 1. Burst Mode Operation

where f

is in MHz, and C

OUT1

is the recommended output

capacitance in μF. Use X5R or X7R types. This choice will

provide low output ripple and good transient response.

Transient performance can be improved with a higher value

capacitor if combined with a phase lead capacitor (typically

22pF) between the output and pin FB1. Note that a larger

phase lead capacitor should be used with a large output

capacitor. A lower value of output capacitor can be used to

save space and cost but transient performance will suffer.

When choosing a capacitor, look carefully through the

data sheet to find out what the actual capacitance is under

operating conditions (applied voltage and temperature).

A physically larger capacitor, or one with a higher voltage

rating, may be required. Table 3 lists several capacitor

vendors.

Table 3: Capacitor Vendors

VENDOR URL

Panasonic www.panasonic.com

Kemet www.kemet.com

Sanyo www.sanyovideo.com

Murata www.murata.com

AVX www.avxcorp.com

Taiyo Yuden www.taiyo-yuden.com

Audible Noise

Ceramic capacitors are small, robust and have very

low ESR. However, ceramic capacitors can sometimes

cause problems when used with the LT3667 due to their

piezoelectric nature. When in Burst Mode operation, the

LT3667’s switching frequency depends on the load current,

and at very light loads the LT3667 can excite the ceramic

capacitor at audio frequencies, generating audible noise.

Since the LT3667 operates at a lower current limit during

Burst Mode operation, the noise is typically very quiet. If

this is unacceptable, use a high performance tantalum or

electrolytic capacitor at the output.

Low Ripple Burst Mode Operation

To enhance efficiency at light loads, the LT3667 oper

ates in low ripple Burst Mode operation which keeps

the

output capacitor charged to the proper voltage while

minimizing the input quiescent current. During Burst Mode

operation, the LT3667 delivers single cycle bursts of

current to the output capacitor followed by sleep periods

where the output power is delivered to the load by the

output capacitor. Because the LT3667 delivers power

to the output

with single, low current pulses, the output

ripple

is kept below 5mV for a typical application. As the

load current decreases towards a no load condition, the

percentage of time that the LT3667 operates in sleep mode

increases and the average input current is greatly reduced

resulting in high efficiency even at very low loads. Note

that during Burst Mode operation, the switching frequency

will be lower than the programmed switching frequency.

At higher output loads (above ~50mA for the front page

application) the LT3667 will be running at the frequency

programmed by the R

resistor, and will be operating in

standard PWM mode. The transition between PWM and

low ripple Burst Mode operation is seamless, and will not

disturb the output voltage.

3667 F01

1µs/DIV

FRONT PAGE APPLICATION

5V/DIV

OUT1

5mV/DIV

100mA/DIV

LOAD

= 10mA

LT3667

3667fb

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APPLICATIONS INFORMATION

BOOST and BD, IN3/BD Pin Considerations

Capacitor C2 and the internal boost Schottky diode (see the

Block Diagram) are used to generate a boost voltage that

is higher than the input voltage. In most cases a 0.22μF

capacitor will work well. Figure 2 shows two ways to ar

range the

boost circuit. The BOOST pin must be more than

1.9V

above the SW pin for best efficiency. For outputs of

2.2V and above, the standard circuit (Figure 2a) is best.

For outputs between 2.2V and 2.5V, use a 0.47μF boost

capacitor. For output voltages below 2.2V, the boost diode

can be tied to the input (Figure 2b), or to another external

supply greater than 2.2V. However, the circuit in Figure 2a

is more efficient because the BOOST pin current and BD

pin quiescent current come from a lower voltage source.

Also, be sure that the maximum voltage ratings of the

BOOST and BD pins are not exceeded.

The minimum operating voltage of an LT3667 applica

tion is limited by the minimum input voltage (4.3V) and

by the maximum duty cycle as outlined in a previous

section. For proper start-up, the minimum input voltage

is also limited

by the boost circuit. If the input voltage

is ramped slowly, the boost capacitor may not be fully

charged. Because the boost capacitor is charged with the

energy stored in the inductor, the circuit relies on some

minimum load current to get the boost circuit running

properly. This minimum load depends on input and output

voltages, and on the arrangement of the boost circuit. The

minimum load generally goes to zero once the circuit has

started. Figure3 shows a plot of minimum load to start

and to run as a function of input voltage. In many cases

the discharged output capacitor will present a load to the

switcher, which will allow it to start. The plots show the

worst-case situation where V

IN1

is ramping very slowly.

For lower start-up voltage, the boost diode can be tied to

IN1

; however, this restricts the input range to one-half of

the absolute maximum rating of the BOOST pin.

Figure 2. Two Circuits for Generating the Boost Voltage

LT3667

(2a) For V

OUT1

≥ 2.2V

BOOSTIN1

IN1

OUT1

GND

LT3667

(2b) For V

OUT1

< 2.2V; V

IN1

< 25V

BOOSTIN1

IN1

3667 F02

OUT1

GND

Figure 3. The Minimum Input Voltage Depends on

Output Voltage, Load Current and Boost Circuit

LOAD CURRENT I

OUT1

(mA)

INPUT VOLTAGE V

IN1

(V)

4.0

4.5

5.0

150 250 400

3667 F03a

3.5

3.0

3.5

50 100

200

300 350

TO START

TO RUN

FRONT PAGE APPLICATION

= V

IN1

, V

OUT1

= 3.3V

LOAD CURRENT I

OUT1

(mA)

INPUT VOLTAGE V

IN1

(V)

5.5

6.0

6.5

150 250 400

3667 F03b

5.0

4.5

4.0

50 100

200

300 350

TO START

TO RUN

FRONT PAGE APPLICATION

= V

IN1

, V

OUT1

= 5V

LT3667

3667fb

For more information www.linear.com/LT3667

APPLICATIONS INFORMATION

Synchronization (QFN Only)

Synchronizing the oscillator of the LT3667 to an external

frequency can be done by connecting a digital clock signal

to the SYNC pin. The LT3667 then synchronizes its SW

node to the rising edge of this clock signal, as shown in

Figure 4. The square wave amplitude should have valleys

that are below 0.5V and peaks that are above 1.2V (up to

6V), and its on-time and off-time should not fall below

50ns. There is a time delay of typically 280ns between the

rising edge of SYNC and the rising edge of SW which is

in part caused by the minimum switch off-time. The fall

ing edge

of SW is sensitive to the falling edge of SYNC,

is therefore recommended to adjust the duty cycle of

the SYNC clock signal accordingly to keep its on-time as

short as possible. Alternatively, AC coupling as shown in

Figure 5 can be used to shorten the clock signal's on-time.

from SYNC to ground which will draw current.

The LT3667 may be synchronized over a 300kHz to 2.2MHz

range. The R

resistor should be chosen to set the switching

frequency 20% below the lowest synchronization input.

For

example, if the synchronization signal is 360kHz, R

should be chosen for 300kHz. Since R

also sets the slope

compensation which avoids subharmonic oscillations, the

minimum inductor value must be calculated using the

frequency determined by R

UVLO1 Pin (QFN Only)

The switching regulator part of the LT3667 can be indepen

dently disabled via the UVLO1 pin. The falling threshold of

the UVLO1 comparator is 1V, with a 75mV hysteresis. The

UVLO1 pin has no effect if V

IN1

and V

IN2

are below 4.3V,

because then the internal undervoltage lockout keeps the

LT3667 shut down anyway.

Adding a resistive divider from IN1 to UVLO1 as shown

in Figure 6 programs the LT3667 to enable the switching

regulator only when V

IN1

is above a certain threshold

voltage V

IN(UVLO1)

, given by:

IN(UVLO1)

R1+R2

•1V

Note that due to the comparator’s hysteresis, the switching

regulator will not be enabled until the input rises slightly

above V

IN(UVLO1)

Figure 6. UVLO1 Pin Allows Programmable Undervoltage

Lockout or Independent Disable of the Switching Regulator

3667 F04

200ns/DIV

SYNC

2V/DIV

RINSING

SYNC

TRIGGERS

5V/DIV

FRONT PAGE APPLICATION

SYNC

10k

3667 F05

10pF

3.3V

LT3667

GND

Figure 4. Synchronization Waveforms

Figure 5. Example of AC Coupling of SYNC Clock Signal

The LT3667 still enters Burst Mode operation at low

output loads while synchronized to an external clock, but

the burst pulses are synchronized to that clock signal. If

synchronization is not needed, the SYNC pin should be

grounded. It may also be tied to a voltage above 1.2V

(logic high), but note that there is an internal 4M resistor

–

SWITCHING

REGULATOR

SHUT DOWN

UVLO1

LT3667

IN1

3667 F06

Shorted and Reversed Input Protection

If the inductor is chosen so that it won’t saturate exces-

sively, the

switching regulator will tolerate a shorted

output.

There is another situation to consider in systems

where the output will be held high when the input to the

LT3667 is absent. This may occur in battery charging

applications or

in battery backup systems where a battery

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LT3667HUDD#PBF

Mfr. #:

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators 40V 400mA Step-Down Switching Regulator with Dual Fault Protected LDOs

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LT3667HUDD#PBF

LT3667HUDD#PBF

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