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CSPU877DBVG8

P1-P3P4-P6P7-P9P10-P12P13-P13
10
COMMERCIAL TEMPERATURE RANGE
IDTCSPU877D
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
TEST CIRCUIT AND SWITCHING WAVEFORMS
Dynamic Phase Offset
FBIN
CLK
t(Ø)DYN
t(Ø)
t(Ø)DYN
SSC ON
SSC OFF
CLK
FBIN
t(Ø)DYN
t(Ø)
t(Ø)DYN
SSC ON
SSC OFF
OE
Y/Y
OE
50% V
DDQ
tEN
50% VDDQ
50% VDDQ
tDIS
50% VDDQ
Y
Y
Y
Y
Time Delay Between Output Enable (OE) and Clock Output (Y, Y)
11
IDTCSPU877D
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
Input and Output Slew Rates
Clock Inputs and
Outputs, OE
80%
20%
V
ID, VOD
tR(I), tR(O)
80%
20%
V20%
V80%
tSLF(I/O)
=
tF(I/O)
tF(I), tF(O)
V20%
V80%
tSLR(I/O)
=
tR(I/O)
APPLICATION INFORMATION
Clock Loading on the PLL outputs (pF)
Clock Structure # of SDRAM Loads per Clock Min. Max.
#1 2 3 5
#2 4 6 10
TEST CIRCUIT AND SWITCHING WAVEFORMS
VDDQ
GND
VIA
CARD
VIA
CARD
BEAD
0603
4.7uF
1206
0.1uF
0603
2200pF
0603
AVDD
AGND
V
DDQ
GND
CSPU877D
1Ω
1
0.1uF
0603
10
Recommended Filtering for the Analog and Digital Power Supplies (AVDD and VDDQ)
NOTES:
Place all decoupling capacitors as close to the CSPU877D pins as possible.
Use wide traces for AVDD and AGND.
Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8Ω DC max., 600Ω at 100MHz).
12
COMMERCIAL TEMPERATURE RANGE
IDTCSPU877D
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
APPLICATION INFORMATION
Clock Structure 1
Clock Structure 2
CSPU877D
C = 10pF
R = 120Ω
FBIN
FBIN
C = 10pF
R = 120Ω
CLK
CLK
Feedbac
k
path
R = 120Ω
Z = 60Ω
Z = 60Ω
8 more
SDRAM
SDRAM
~2.5"
~0.3"
~0.6" (split to terminator)
CSPU877D
C = 10pF
R = 120Ω
FBIN
FBIN
C = 10pF
R = 120Ω
CLK
CLK
Feedback path
R = 120Ω
Z = 60Ω
Z = 60Ω
8 more
SDRAM
SDRAM
~2.5"
~0.3"
~0.6" (split to terminator)
SDRAM
SDRAM
Stacked
Stacked
P1-P3P4-P6P7-P9P10-P12P13-P13

CSPU877DBVG8

Mfr. #:
Buy CSPU877DBVG8
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1.8V PLL Differ 1:10 DDR 2 Clock Driver
Lifecycle:
New from this manufacturer.
Delivery:
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