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XRT91L33IGTR-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
AUG 2008 REV. V1.0.0
FEATURES
• Performs clock and data recovery for selectable
data of 622.08 Mbps (STS-12/STM-4) or 155.52
Mbps (STS-3/STM-1) NRZ data
• Meets Telcordia, ANSI and ITU-T G.783 and G.825
SDH jitter requirements including T1.105.03 - 2002
SONET Jitter Tolerance specification, and GR-253
CORE, GR-253 ILR SONET Jitter specifications.
• Lock output pin monitors data run length and
frequency drift from reference clock
• Data is resampled at the output
• Active High Signal Detect (SIGD) LVPECL input
• Low jitter, high-speed outputs support LVPECL and
low-power LVDS termination
• 19.44 MHz reference frequency LVTTL input
• Low power: 215 mW typical
• 3.3V power supply
• 20-pin TSSOP package
• Requires one external capacitor
• PLL bypass operation facilitates board debug
process
• ESD greater than 2kV on all pins
APPLICATIONS
• SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS
• SONET/SDH Test Equipment
• DWDM Termination Equipment
GENERAL DESCRIPTION
The XRT91L33 is a fully integrated multirate Clock
and Data Recovery (CDR) device for SONET/SDH
622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/
STM-1 applications. The device provides Clock and
Data Recovery (CDR) function by synchronizing its
on-chip Voltage Controlled Oscillator (VCO) to the
incoming serial scrambled non-return to zero (NRZ)
data stream.
Figure 1 shows the block diagram of
the XRT91L33.
FIGURE 1. BLOCK DIAGRAM OF XRT91L33
RXDOP
RXDON
RXCLKOP
RXCLKON
LOCK
LVDS/LVPECL
Output Drivers
CDR
RECVD-
DATAOUT
RECVD-
CLKOUT
STS-12/3
or
STM-4/1
Clock and Data
Recovery
Differential
Receiver
RXDIP
RXDIN
RXDATAIN
RX LOOP
FILTER
SIGD
LCKTOREFN
1
0
PLL
STS12_MODE
REFCK
19.44 MHz
TEST
Internal
biasing
External
100R
termination
1u F
MUTE
RXDO
CAP+
CAP+
XRT91L33
2
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT REV. V1.0.0
CLOCK AND DATA RECOVERY OVERVIEW
The clock and data recovery (CDR) unit accepts high speed NRZ serial data from the Differential receiver and
generates a clock with a frequency equal to that of the incoming data. The CDR block uses a reference clock to
train and monitor its clock recovery PLL. Upon startup, the PLL locks to the local reference clock. Once this is
achieved, the PLL attempts to lock onto the incoming receive serial data stream. Whenever the recovered
clock frequency deviates from the local reference clock frequency by more than approximately ±500 ppm, the
clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock.
Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock
(based on the local reference) to the framer/mapper device. An LOS condition occurs when either SIGD or
LCKTOREFN is low. In this case, the receive serial data output is forced to a logic zero state for the entire
duration of the LOS condition. This acts as a receive data mute upon LOS function to prevent random noise
from being misinterpreted as valid incoming data. When SIGD becomes active again, the recovered clock is
determined to be within ±500 ppm accuracy with respect to the local reference source and LOS is no longer
declared, the clock recovery PLL will switch and lock back onto the incoming receive serial data stream.
FIGURE 2. 20 PIN TSSOP OF XRT91L33 (TOP VIEW)
TABLE 1: ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT91L33IG 20-pin TSSOP Package
-40
°
C to +85
°
C
XRT91L33IG-F 20-Pin TSSOP Lead-Free Package
-40
°
C to +85
°
C
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDA
RXDIP
RXDIN
VSSA
LOCK
STS12_MODE
REFCK
LCKTOREFN
VSS
VDD
VDDA
VSSA
CAP+
CAP-
TEST
SIGD
RXDOP
RXDON
RXCLKOP
RXCLKON
XRT91L33
3
REV. V1.0.0 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FEATURES......................................................................................................................... 1
APPLICATIONS ................................................................................................................. 1
GENERAL DESCRIPTION................................................................................................. 1
FIGURE 1. BLOCK DIAGRAM OF XRT91L33 ...................................................................................................................................... 1
CLOCK AND DATA RECOVERY OVERVIEW .......................................................................................................2
FIGURE 2. 20 PIN TSSOP OF XRT91L33 (TOP VIEW).................................................................................................................... 2
T
ABLE 1: ORDERING INFORMATION................................................................................................................................................... 2
1.0 PIN DESCRIPTIONS ..............................................................................................................................4
TABLE 2: PIN DESCRIPTION TABLE ................................................................................................................................................... 4
..................................................................................................................................................................... 5
2.0 FUNCTIONAL DESCRIPTION ............................................................................................................... 6
2.1 REFERENCE CLOCK INPUT ........................................................................................................................... 6
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................... 6
2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITOR ....................................................................................... 6
2.4 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ........................................................................... 6
2.5 SIGNAL DETECTION ....................................................................................................................................... 6
FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION ............................................................ 7
2.6 LOCK DETECTION ........................................................................................................................................... 7
2.7 PLL TEST OPERATION ................................................................................................................................... 7
TABLE 3: SIGNAL DETECT AND PLL TEST OPERATION CONTROL .................................................................................................... 8
3.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 9
3.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 9
TABLE 4: ABSOLUTE MAXIMUM RATINGS........................................................................................................................................... 9
3.2 OPERATING CONDITIONS .............................................................................................................................. 9
TABLE 5: RECOMMENDED OPERATING CONDITIONS .......................................................................................................................... 9
3.3 LVPECL SINGLE ENDED INPUT AND OUTPUT DC CHARACTERISTICS .................................................. 9
TABLE 6: LVPECL SINGLE ENDED INPUTS AND OUTPUTS................................................................................................................. 9
3.4 LVPECL DIFFERENTIAL INPUT AND OUTPUT DC CHARACTERISTICS ................................................. 10
TABLE 7: LVPECL DIFFERENTIAL INPUTS AND OUPUTS .................................................................................................................. 10
F
IGURE 4. DIFFERENTIAL VOLTAGE SWING DEFINITIONS (INPUT OR OUTPUT) FOR CLOCK AND DATA ................................................... 10
T
ABLE 8: LVDS OUTPUTS............................................................................................................................................................. 10
T
ABLE 9: LVTTL INPUTS................................................................................................................................................................ 11
3.5 AC CHARACTERISTICS ................................................................................................................................ 11
TABLE 10: PERFORMANCE SPECIFICATIONS.................................................................................................................................... 11
4.0 JITTER PERFORMANCE .................................................................................................................... 12
4.1 SONET JITTER REQUIREMENTS ................................................................................................................. 12
4.1.1 RX JITTER TOLERANCE:.......................................................................................................................................... 12
F
IGURE 5. GR-253/G.783 JITTER TOLERANCE MASK ..................................................................................................................... 12
F
IGURE 6. XRT91L33 JITTER TOLERANCE AT 155 MBPS OC3/STM-1.......................................................................................... 13
F
IGURE 7. XRT91L33 JITTER TOLERANCE AT 622 MBPS OC12/STM-4........................................................................................ 13
4.1.2 JITTER GENERATION................................................................................................................................................ 13
5.0 HIGH-SPEED OUTPUTS ..................................................................................................................... 14
FIGURE 8. HIGH SPEED OUTPUTS, LVDS TERMINATION.................................................................................................................. 14
F
IGURE 9. HIGH-SPEED OUTPUTS, LVPECL TERMINATION OPTIONS ............................................................................................... 14
6.0 RESAMPLED DATA AND CLOCK OUTPUTS .................................................................................. 15
FIGURE 10. OUTPUT DATA AND CLOCK AFTER RESAMPLING............................................................................................................ 15
T
ABLE 11: OUTPUT TIMING ............................................................................................................................................................ 15
7.0 PACKAGE DIMENSIONS .................................................................................................................... 16
TABLE 12: REVISION HISTORY........................................................................................................................................................ 16
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

XRT91L33IGTR-F

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Description:
Clock Generators & Support Products Recovery Unit
Lifecycle:
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