ADM8323/ADM8324 Data Sheet
Rev. A | Page 10 of 16
THEORY OF OPERATION
CIRCUIT DESCRIPTION
The ADM8323/ADM8324 provide microprocessor supply
voltage supervision by controlling the microprocessor reset input.
Code execution errors are avoided during power-up, power-down,
and brownout conditions by asserting a reset signal when the
supply voltage is below a preset threshold and by allowing supply
voltage stabilization with a fixed timeout reset pulse after the
supply voltage rises above the threshold. In addition, problems with
microprocessor code execution can be monitored and corrected
with a windowed watchdog timer. If the user detects a problem
with system operation, a manual reset input is available to reset
the microprocessor, for example, by means of an external push-
button switch.
PUSH-PULL
RESET
OUTPUT
The ADM8323 features an active low push-pull reset output.
The reset signal is guaranteed to be valid for V
CC
down to 0.9 V.
The reset output is asserted when V
CC
is below the reset thresh-
old (V
TH
), when
MR
is driven low, or when WDI is not serviced
within the watchdog timeout window. Reset remains asserted for
the duration of the reset active timeout period (t
RP
) after V
CC
rises
above the reset threshold and
MR
transitions from low to high or
after the watchdog timer fault occurs.
Figure 20 illustrates the
behavior of the reset output.
V
CC
1V
V
CC
0V
V
TH
V
TH
0V
V
CC
RESET
t
RD
t
RP
11802-009
Figure 20. Reset Timing Diagram
OPEN-DRAIN
RESET
OUTPUT
The ADM8324 has an active low, open-drain reset output. This
output structure requires an external pull-up resistor to connect
the reset output to a voltage rail no higher than Vcc. Use a resistor
that complies with the logic low and logic high voltage level
requirements of the microprocessor while supplying input current
and leakage paths on the
RESET
line. A 10 kΩ resistor is adequate
in most situations.
MANUAL RESET INPUT
The ADM8323/ADM8324 feature a manual reset input (
MR
),
which when driven low, asserts the reset output. When
MR
transitions from low to high, the reset output remains asserted for
the duration of the reset active timeout period before deasserting.
The
MR
input has a 75 kΩ, internal pull-up resistor so that the
input is always high when unconnected. An external push-button
switch can be connected between
MR
and ground so the user
can generate a reset. Debounce circuitry for this purpose is
integrated on chip.
Noise immunity is provided on the
MR
input, and fast, negative
going transients of up to 100 ns (typical) are ignored. A 0.1 µF
capacitor between
MR
and ground provides additional noise
immunity.
WINDOWED WATCHDOG INPUT
The ADM8323/ADM8324 feature a windowed watchdog timer
that monitors microprocessor activity. A timer circuit is cleared
with every high to low logic transition on the watchdog input pin
(WDI), which detects pulses as short as 200 ns. If this watchdog
pulse does not occur within the defined time window, a reset
asserts. Failure of the microprocessor to toggle WDI within the
watchdog window indicates a code execution error and, therefore,
the generated reset pulse restarts the microprocessor in a
known state.
As well as logic transitions on WDI, the watchdog timer is also
cleared by a reset assertion due to an undervoltage condition on
V
CC
or due to
MR
being pulled low. When a reset is asserted, the
watchdog timer is cleared and does not begin counting again until
the reset deasserts. The windowed watchdog timer cannot
be disabled.
All WDI input pulses are ignored while a reset is asserted. After
the reset deasserts, the first WDI falling edge is ignored for the
fast fault condition.
11802-010
WDI
RESET
t
RP
t
WDI
< t
WD-FASTmin
Figure 21. Watchdog Fast Timeout Fault
11802-011
WDI
RESET
t
WDI
> t
WD-SLOWmax
t
RP
Figure 22. Watchdog Slow Timeout Fault
11802-012
WDI
RESET
t
WD-FASTmax
< t
WDI
< t
WD-SLOWmin
Figure 23. Normal Watchdog Operation
