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CY26049ZXI-36

P1-P3P4-P6P7-P7
FailSafe™ PacketClock™ Global Communications
Clock Generator
CY26049-36
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07415 Rev. *C Revised July 16, 2004
Features
• Fully integrated phase-locked loop (PLL)
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• Output frequencies selectable and/or programmed to
standard communication frequencies
• Low-jitter, high-accuracy outputs
• Commercial and Industrial operation
• 3.3V ± 5% operation
• 16-lead TSSOP
Benefits
• Integrated high-performance PLL tailored for telecom-
munications frequency synthesis eliminates the need
for external loop filter components
• When reference is in range, SAFE pin is driven high.
• When reference is off, DCXO maintains clock outputs.
SAFE pin is low.
• DCXO maintains continuous operation should the input
reference clock fail
• Glitch-free transition simplifies system design
• Selectable output clock rates include T1/DS1, E1,
T3/DS3, E3, and OC-3.
• Works with commonly available, low-cost 18.432-MHz
crystal
• Zero-ppm error for all output frequencies
• Performance guaranteed for applications that require
an extended temperature range
• Compatible across industry standard design platforms
• Industry standard package with 6.4 x 5.0 mm
2
footprint
and a height profile of just 1.1 mm.
Logic Block Diagram
CLK/2
FS[3:0]
XIN
XOUT
ICLK
CLK
SAFE
frequency selec
t
Input reference
(typical 8 kHz)
external pullable crystal
(18.432 MHz)
8K
DIGITAL
CONTROLLED
CRYSTAL
OSCILLATOR
FAILSAFE
TM
CONTROL
PHASE
LOCKED
LOOP
OUTPUT
DIVIDERS
High=ICLK detected
Pin Configuration
CY26049-36
16-pin TSSOP
Top View
ICLK 1 16 NC
8K 2 15 CLK
FS1 3 14 FS0
FS2 4 13 FS3
VDD 5 12 VDD
VSS 6 11 VSS
CLK/2 7 10 SAFE
XIN 8 9 XOUT
CY26049-36
Document #: 38-07415 Rev. *C Page 2 of 7
Functional Description
CY26049 is a FailSafe frequency synthesizer with a reference
clock input and three clock outputs. The device provides an
optimum solution for applications where continuous operation
is required in the event of a primary clock failure. The
continuous, glitch-free operation is achieved by using a DCXO
which serves as a primary clock source. The FailSafe control
circuit synchronizes the DCXO with the reference as long as
the reference is within the pull range of the crystal.
In the event of a reference clock failure the DCXO maintains
the last frequency and phase information of the reference
clock. The unique feature of the CY26049-36 is that the DCXO
is in fact the primary clocking source. When the reference
clock is restored, the DCXO automatically re-synchronizes to
the reference. The status of the reference clock input, as
detected by the CY26049-36, is reported by the SAFE pin.
In the buffer mode (FS3:FS0 = 1110 or 1111), the CY26049-36
can be used as a jitter attenuator. In this mode, extensive jitter
on the input clock will be “filtered”, resulting in a low-jitter
output clock.
Pin Definitions
Pin Name Pin Number Pin Description
ICLK 1 Reference Input Clock; 8 kHz or 10 to 60 MHz.
8K 2 Clock Output; 8 kHz or high impedance in buffer mode.
FS1 3 Frequency Select 1; Determines CLK outputs per Tab le 1.
FS2 4 Frequency Select 2; Determines CLK outputs per Tab le 1.
VDD 5 Voltage Supply; 3.3V.
VSS 6 Ground
CLK/2 7 Clock Output; Frequency per Table 1.
XIN 8 Pullable Crystal Input; 18.432 MHz.
XOUT 9 Pullable Crystal Output; 18.432 MHz.
SAFE 10 High = reference ICLK within range, Low = reference ICLK out of range.
VSS 11 Ground
VDD 12 Voltage Supply; 3.3V.
FS3 13 Frequency Select 3; Determines CLK outputs per Tab le 1.
FS0 14 Frequency Select 0; Determines CLK outputs per Tab le 1.
CLK 15 Clock Output; Frequency per Table 1.
NC 16 No Connect
Selector Guide
Part Number Input Frequency Range Outputs Output Frequencies
CY26049-36 8 kHz or 10 to 60 MHz Reference Input
Crystal: 18.432-MHz pullable Crystal per Cypress Specification
3 8 kHz to 155.52 MHz
Selectable (see Table 1)
CY26049-36
Document #: 38-07415 Rev. *C Page 3 of 7
Frequency Select Tables
Table 1. CY26049-36 Frequency Select–Output Decoding Table–External Mode (MHz except as noted)
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8K Crystal
8 kHz 0 0 0 0 1.544 3.088 8 kHz 18.432
8 kHz 0 0 0 1 2.048 4.096 8 kHz 18.432
8 kHz 0 0 1 0 22.368 44.736 8 kHz 18.432
8 kHz 0 0 1 1 17.184 34.368 8 kHz 18.432
8 kHz 0 1 0 0 77.76 155.52 8 kHz 18.432
8 kHz 0 1 0 1 16.384 32.768 8 kHz 18.432
8 kHz 0 1 1 0 14.352 28.704 8 kHz 18.432
8 kHz 0 1 1 1 High Z
[1]
High Z
[1]
High Z
[1]
18.432
8 kHz 1 0 0 0 18.528 37.056 8 kHz 18.432
8 kHz 1 0 0 1 12.352 24.704 8 kHz 18.432
8 kHz 1 0 1 0 7.68 15.36 8 kHz 18.432
8 kHz 1 0 1 1 High Z
[1]
High Z
[1]
High Z
[1]
18.432
8 kHz 1 1 0 0 12.288 24.576 8 kHz 18.432
8 kHz 1 1 0 1 16.384 32.768 8 kHz 18.432
Table 2. CY26049-36 Frequency Select–Output Decoding Table–Buffer Mode
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8K Crystal
20 to 60 1 1 1 0 ICLK/2 ICLK High Z
[1]
ICLK/2
10 to 30 1 1 1 1 2*ICLK 4*ICLK High Z
[1]
ICLK
Note:
1. High Z = high impedance.
P1-P3P4-P6P7-P7

CY26049ZXI-36

Mfr. #:
Buy CY26049ZXI-36
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL FailSafe Clock IND
Lifecycle:
New from this manufacturer.
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