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74LV08PW-Q100,118

P1-P3P4-P5
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 0
1 Publication Order Number:
NL17SHT00/D
NL17SHT00
Single 2-Input NAND Gate/
CMOS Logic Level Shifter
LSTTL−Compatible Inputs
The NL17SHT00 is a single gate 2−input NAND fabricated with
silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the high voltage power supply.
The NL17SHT00 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
NL17SHT00 to be used to interface 5 V circuits to 3 V circuits. The
output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
• High Speed: t
PD
= 3.1 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 1 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2 V
• CMOS−Compatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1 V
CC
@Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• These are Pb−Free Devices
V
CC
IN B
IN A
OUT Y
GND
IN A
OUT Y
&
IN B
Figure 1. Pinout
Figure 2. Logic Symbol
1
2
3
4
5
PIN ASSIGNMENT
1
2
3IN B
IN A
GND
4
5V
CC
OUT Y
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
H
H
H
L
Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
SOT−953
CASE 527AE
K = Specific Device Code
M = Month Code
KM
1
NL17SHT00
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Characteristics Value Unit
V
CC
DC Supply Voltage −0.5 to +7.0 V
V
IN
DC Input Voltage −0.5 to +7.0 V
V
OUT
DC Output Voltage V
CC
= 0
High or Low State
−0.5 to 7.0
−0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current V
OUT
< GND; V
OUT
> V
CC
±20 mA
I
OUT
DC Output Current ±25 mA
I
CC
DC Supply Current, V
CC
and GND 50 mA
T
STG
Storage Temperature Range *65 to )150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature Under Bias )150
_C
P
D
Power Dissipation in Still Air at 85_C
50 mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 125_C (Note 1)
±100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 3.0 5.5 V
V
IN
DC Input Voltage 0.0 5.5 V
V
OUT
DC Output Voltage V
CC
= 0
High or Low State
0.0
0.0
5.5
V
CC
V
T
A
Operating Temperature Range −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3 V ± 0.3 V
V
CC
= 5.0 V ± 0.5 V
0
0
100
20
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100
1000
TIME, YEARS
NORMALIZED FAILURE RATE
T
J
= 130 C°
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
T
J
=120 C°
T
J
=110 C°
T
J
=100 C°
T
J
= 90 C°
T
J
= 80 C°
NL17SHT00
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
(V)
T
A
= 25°C T
A
≤ 85°C −55 ≤ T
A
≤ 125°C
Unit
Min Typ Max Min Max Min Max
V
IH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
V
IL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= −50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= −4 mA
I
OH
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50 mA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
I
IN
Maximum Input
Leakage Current
V
IN
= 5.5 V or GND 0 to
5.5
±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent
Supply Current
V
IN
= V
CC
or GND 5.5 1.0 20 40
mA
I
CCT
Quiescent Supply
Current
Input: V
IN
= 3.4 V 5.5 1.35 1.50 1.65 mA
I
OFF
Power Off Output
Leakage Current
V
OUT
= 5.5 V 0.0 0.5 5.0 10
mA
AC ELECTRICAL CHARACTERISTICS Input t
r
= t
f
= 3.0 ns
Symbol
Parameter Test Conditions
T
A
= 25°C T
A
≤ 85°C −55 ≤ T
A
≤ 125°C
Unit
Min Typ Max Min Max Min Max
t
PLH
,
t
PHL
Maximum Propagation
Delay, Input A or B to Y
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
C
L
= 50 pF
4.1
5.5
10.0
13.5
11.0
15.0
13.0
17.5
ns
V
CC
= 5.0 ± 0.5 V C
L
= 15 pF
C
L
= 50 pF
3.1
3.6
6.9
7.9
8.0
9.0
9.5
10.5
C
IN
Maximum Input
Capacitance
5.5 10 10 10 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0 V
pF
11
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
P1-P3P4-P5

74LV08PW-Q100,118

Mfr. #:
Buy 74LV08PW-Q100,118
Manufacturer:
Nexperia
Description:
Logic Gates 74LV08PW-Q100/TSSOP14/REEL 13
Lifecycle:
New from this manufacturer.
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