ISL96017
4
FN8243.2
June 8, 2012
TC
V
(Note 11, 17)
Ratiometric Temperature
Coefficient
DCP Register between 10 hex and 6F hex ±4 ppm/°C
DNL (Note 6, 9) Differential Non-Linearity Monotonic over all tap positions -0.75 0.75 LSB
INL (Note 6, 10) Integral Non-Linearity -1 1 LSB
DCP IN RESISTOR MODE (Measurements between RH and RW with RL not connected)
R
127
(Note 12) Resistance Offset. U version - DCP Register set to 7F hex.
Measured between R
H
and R
W
pins.
0 0.5 2 MI
W version - DCP Register set to 7F hex.
Measured between R
H
and R
W
pins.
1 5 MI
TC
R
(Note 15,17)
Resistance Temperature Coefficient ±100 ppm/°C
RDNL
(Note 12,13)
Resistance Differential Non-Linearity -0.75 0.75 MI
(Note 1)
RINL
(Note 12,14)
Resistance Integral Non-Linearity -1 1 MI
(Note 1)
EEPROM SPECS
EEPROM Endurance 1,000,000 Cycles
EEPROM Retention At 55°C 50 Years
t
WC
(Note 16) Non-Volatile Write Cycle Time 6 12 ms
SERIAL INTERFACE SPECS
V
IL
WP, SDA, and SCL Input Buffer LOW Voltage -0.3 0.3*
VDD
V
V
IH
WP, SDA and SCL Input Buffer HIGH Voltage 0.7*
VDD
VDD
+0.3
V
Hysteresis SDA and SCL Input Buffer Hysteresis 0.05*
VDD
V
V
OL
SDA Output Buffer LOW Voltage, Sinking
4mA
00.4V
Cpin WP
, SDA, and SCL Pin Capacitance 10 pF
f
SCL
SCL Frequency 400 kHz
t
IN
Pulse Width Suppression Time at SDA and
SCL Inputs.
Any pulse narrower than the max spec is
suppressed
50 ns
t
AA
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window
900 ns
t
BUF
Time the Bus Must be Free Before the Start of
a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VDD during
the following START condition
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of VDD crossing 1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of VDD crossing 600 ns
t
SU:STA
START Condition Setup Time SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge crossing 30% of VDD to
SCL falling edge crossing 70% of VDD
600 ns
Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 18)
TYP
(Note 5)
MAX
(Note 18) UNIT
ISL96017
5
FN8243.2
June 8, 2012
t
SU:DAT
Input Data Setup Time From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
100 ns
t
HD:DAT
Input Data Hold Time From SCL rising edge crossing 70% of VDD to
SDA entering the 30% to 70% of VDD window
0 ns
t
SU:STO
STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VDD
600 ns
t
HD:STO
STOP Condition Hold Time From SDA rising edge to SCL falling edge. Both
crossing 70% of VDD
600 ns
t
DH
Output Data Hold Time From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window
0 ns
t
R
SDA and SCL Rise Time From 30% to 70% of VDD 20+
0.1*Cb
250 ns
t
F
SDA and SCL Fall Time From 70% to 30% of VDD 20+
0.1*Cb
250 ns
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF
Rpu SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by t
R
and t
F
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1 k
t
SU:WP
WP Setup Time Before START condition 600 ns
t
HD:WP
WP Hold Time After STOP condition 600 ns
NOTES:
5. Typical values are for T
A
= 25°C and V
DD
= 3.3V.
6. LSB = (V(RW)
127
– V(RW)
0
)/127. V(RW)
127
and V(RW)
0
are the voltage at pin RW for the DCP Register set to 7F hex and 00 hex respectively.
7. FSerror = (V(RW)
127
– VDD)/LSB
8. ZSerror = V(RW)
0
/LSB
9. DNL = [(V(RW)
i
– V(RW)
i-1
)/LSB] – 1, for i from 1 to 127. i is the DCP Register setting.
10. INL = [V(RW)
i
– i * LSB – V(RW)
0
]/LSB, for I = 1 to 127.
11. for i = 16 to 111, and T = -40°C to 85°C
12. MI = (R
0
– R
127
)/127. MI is minimum increment. R
0
and R
127
are the resistances between RH and RW with the DCP Register set to 00 hex and 7F
hex, respectively.
13. RDNL = (R
i
– R
i-1
)/MI – 1, for i from 1 to 111. i is the DCP Register setting.
14. RINL = [R
i
– (MI * i) – R
127
]/MI, for i from 1 to 111.
15. ; for i = 1 to 111, and T = -40°C to 85°C
16. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid
STOP condition at the end of a Write sequence of a I
2
C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
17. Parameter is not 100% tested.
18. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical Specifications Over recommended operating conditions unless otherwise stated. All voltages with respect to GND. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 18)
TYP
(Note 5)
MAX
(Note 18) UNIT
TC
V
Max V RWiMin V RWi
Max V RWiMin V RWi+2
-----------------------------------------------------------------------------------------------
10
6
125C
-----------------
=
TC
R
Max RiMin Ri
Max RiMin Ri+2
----------------------------------------------------------------
110
6
125C
-------------------
=
ISL96017
6
FN8243.2
June 8, 2012
I
2
C Timing Diagram
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R

ISL96017WIRT8Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs ISL96017W IND 8LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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