A1171EEWLT-P

Micropower Ultrasensitive Hall Effect Switch
A1171
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VDD
NC
V
S
GND
SELECT
VOUTPN
A1171
VOUTPS
Outputs
0.1 µF
C
BYP
VDD
NC
V
S
GND
SELECT
VOUTPN
A1171
VOUTPS
Outputs
0.1 µF
C
BYP
It is strongly recommended that an external bypass capacitor be
connected (in close proximity to the Hall element) between the
supply and ground of the device to reduce both external noise
and noise generated by the chopper stabilization technique. As is
shown in figure 3, a 0.1 μF capacitor is typical.
Extensive applications information on magnets and Hall-effect
devices is available in the following notes:
• Hall-Effect IC Applications Guide, AN27701
• Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead
Welding and Lead Forming AN27703.1
• Soldering Methods for Allegro Products (SMD and Through-
Hole), AN26009
All are provided in Allegro Electronic Data Book, AMS-702,
and on the Allegro Web site, www.allegromicro.com.
Figure 3. Typical Application Circuits: (a) Omnipolar operation, and (b) Unipolar Operation
(a) (b)
Applications
Micropower Ultrasensitive Hall Effect Switch
A1171
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall element. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges.
Chopper stabilization is a unique approach used to minimize
Hall offset on the chip. The Allegro technique, namely Dynamic
Quadrature Offset Cancellation, removes key sources of the
output drift induced by thermal and mechanical stresses.
This offset reduction technique is based on a signal modulation-
demodulation process. The undesired offset signal is separated
from the magnetic field-induced signal in the frequency domain,
through modulation. The subsequent demodulation acts as a
modulation process for the offset, causing the magnetic field
induced signal to recover its original spectrum at baseband,
while the dc offset becomes a high-frequency signal. The mag-
netic sourced signal then can pass through a low-pass filter,
while the modulated dc offset is suppressed. This configuration
is illustrated in figure 4.
The chopper stabilization technique uses a high frequency clock.
For demodulation process, a sample and hold technique is used,
where the sampling is performed at twice the chopper frequency.
This high-frequency operation allows a greater sampling rate,
which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling.
The repeatability of magnetic field-induced switching is affected
slightly by a chopper technique. However, the Allegro high
frequency chopping approach minimizes the affect of jitter and
makes it imperceptible in most applications. Applications that
are more likely to be sensitive to such degradation are those
requiring precise sensing of alternating magnetic fields; for
example, speed sensing of ring-magnet targets. For such applica-
tions, Allegro recommends its digital device families with lower
sensitivity to jitter. For more information on those devices,
contact your Allegro sales representative.
Amp
Regulator
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
Figure 4. Chopper Stabilization Circuit (Dynamic Quadrature Offset Cancellation)
Micropower Ultrasensitive Hall Effect Switch
A1171
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package EW, 6-pin DFN/MLP
SEATING
PLANE
0.38 ±0.02
0.70 ±0.10 1.25 ±0.05
0.25 ±0.05
1.10 ±0.10
1.10
0.30
0.70 1.575
0.50
0.325
2.00 ±0.15
1.50 ±0.15
C0.08
7X
0.325
+0.055
–0.045
0.50 BSC
A
1
1
6
6
1
6
A
Terminal #1 mark area
B
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only, not for tooling use (refernce DWG-2856; similar to
JEDEC Type 1, MO-229X2BCD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
C
Reference land pattern layout (reference IPC7351
SON50P200X200X100-9M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
Active Area Depth 0.15 mm REF
E
E
C
B
Hall Element (not to scale)
F
F
F
F
0.75
1.00
PCB Layout Reference View
C
Branding scale and appearance at supplier discretion
G
G
D
D
Coplanarity includes exposed thermal pad and terminals
Standard Branding Reference View
N = Last two digits of device part number
Y = Last digit of year of manufacture
W = Week of manufacture
NN
YWW
1

A1171EEWLT-P

Mfr. #:
Manufacturer:
Description:
MAGNETIC SWITCH OMNIPOLAR 6DFN
Lifecycle:
New from this manufacturer.
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