Document Number: 001-67798 Rev. *F Page 7 of 16
Switching Characteristics
Over the Operating Range
Parameter
[14]
Description
45 ns
Unit
Min Max
Read Cycle
t
RC
Read cycle time 45 – ns
t
AA
Address to data valid – 45 ns
t
OHA
Data hold from address change 10 – ns
t
ACE
CE
1
LOW/CE
2
HIGH to data valid – 45 ns
t
DOE
OE LOW to data valid – 22 ns
t
LZOE
OE LOW to Low Z
[15]
5 – ns
t
HZOE
OE HIGH to High Z
[15, 16]
– 18 ns
t
LZCE
CE
1
LOW/CE
2
HIGH to Low Z
[15]
10 – ns
t
HZCE
CE
1
HIGH/CE
2
LOW to High Z
[15, 16]
– 18 ns
t
PU
CE
1
LOW/CE
2
HIGH to Power-up 0 – ns
t
PD
CE
1
HIGH/CE
2
LOW to Power-down – 45 ns
t
DBE
BLE/BHE LOW to data valid – 45 ns
t
LZBE
BLE/BHE LOW to Low Z
[15, 17]
5 – ns
t
HZBE
BLE/BHE HIGH to High Z
[15, 16]
– 18 ns
Write Cycle
[18, 19]
t
WC
Write cycle time 45 – ns
t
SCE
CE
1
LOW/CE
2
HIGH to Write End 35 – ns
t
AW
Address setup to write end 35 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 35 – ns
t
BW
BLE/BHE LOW to write end 35 – ns
t
SD
Data setup to write end 25 – ns
t
HD
Data hold from write end 0 – ns
t
HZWE
WE LOW to High Z
[15, 16]
– 18 ns
t
LZWE
WE HIGH to Low Z
[15]
10 – ns
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the Figure 2 on page 5.
15. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
16. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
17. If both byte enables are together, this value is 10 ns.
18. The internal write time of the memory is defined by the overlap of WE
, CE
= V
IL
, BHE, BLE, or both = V
IL
. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width for WRITE Cycle 4 (WE
controlled, OE LOW) should be equal to the sum of t
HZWE
and t
SD
.
