LOC117PTR

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NTEGRATED
C
IRCUITS
D
IVISION
www.ixysic.com
4
R05
LOC117
Manufacturing Information
Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to
the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper
operation of our devices when handled according to the limitations and information in that standard as well as to any
limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture
Sensitivity Level (MSL) classification as shown below, and should be handled according to the requirements of the
latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device Moisture Sensitivity Level (MSL) Classifi cation
LOC117 / LOC117S MSL 1
LOC117P MSL 3
ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
Soldering Profile
Provided in the table below is the Classification Temperature (T
C
) of this product and the maximum dwell time the
body temperature of this device may be above (T
C
- 5)ºC. The classification temperature sets the Maximum Body
Temperature allowed for this device during lead-free reflow processes. For through hole devices, and any other
processes, the guidelines of J-STD-020 must be observed.
Device Classifi cation Temperature (T
C
) Dwell Time (t
p
) Max Refl ow Cycles
LOC117 250ºC
30 seconds
N/A
LOC117S 250ºC3
LOC117P 240ºC3
Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. Board washing to reduce
or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken
to prevent damage to the device. These precautions include, but are not limited to: using a low pressure wash
and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the
washing process. Due to the variability of the wash parameters used to clean the board, determination of the bake
temperature and duration necessary to remove the moisture trapped within the package is the responsibility of the
user (assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not
be used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based.
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NTEGRATED
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IVISION
LOC117
www.ixysic.com
5
R05
Dimensions
mm
(inches)
PCB Hole Pattern
2.540 ± 0.127
(0.100 ± 0.005)
6.350 ± 0.127
(0.250 ± 0.005)
9.144 ± 0.508
(0.360 ± 0.020)
0.457 ± 0.076
(0.018 ± 0.003)
9.652 ± 0.381
(0.380 ± 0.015)
7.239 TYP.
(0.285)
7.620 ± 0.254
(0.300 ± 0.010)
4.064 TYP
(0.160)
0.813 ± 0.102
(0.032 ± 0.004)
8-0.800 DIA.
(8-0.031 DIA.)
2.540 ± 0.127
(0.100 ± 0.005)
7.620 ± 0.127
(0.300 ± 0.005)
7.620 ± 0.127
(0.300 ± 0.005)
6.350 ± 0.127
(0.250 ± 0.005)
3.302 ± 0.051
(0.130 ± 0.002)
Pin 1
0.254 ± 0.0127
(0.010 ± 0.0005)
Dimensions
mm
(inches)
PCB Land Pattern
9.398 ± 0.127
(0.370 ± 0.005)
6.350 ± 0.127
(0.250 ± 0.005)
2.540 ± 0.127
(0.100 ± 0.005)
7.620 ± 0.254
(0.300 ± 0.010)
0 MIN / 0.102 MAX
(0 MIN / 0.004 MAX)
2.286 MAX.
(0.090 MAX.)
0.203 ± 0.013
(0.008 ± 0.0005)
0.635 ± 0.127
(0.025 ± 0.005)
9.652 ± 0.381
(0.380 ± 0.015)
0.457 ± 0.076
(0.018 ± 0.003)
2.159 ± 0.025
(0.085 ± 0.001)
2.54
(0.10)
8.70
(0.3425)
1.55
(0.0610)
0.65
(0.0255)
0.864 ± 0.120
(0.034 ± 0.004)
Pin 1
Dimensions
mm
(inches)
PCB Land Pattern
2.540 ± 0.127
(0.100 ± 0.005)
9.652 ± 0.381
(0.380 ± 0.015)
6.350 ± 0.127
(0.250 ± 0.005)
9.525 ± 0.254
(0.375 ± 0.010)
0.457 ± 0.076
(0.018 ± 0.003)
0.813 ± 0.102
(0.032 ± 0.004)
4.445 ± 0.127
(0.175 ± 0.005)
7.620 ± 0.254
(0.300 ± 0.010)
0.635 ± 0.127
(0.025 ± 0.005)
0.254 ± 0.0127
(0.010 ± 0.0005)
2.54
(0.10)
8.90
(0.3503)
1.65
(0.0649)
0.65
(0.0255)
3.302 ± 0.051
(0.130 ± 0.002)
Pin 1
LOC117
LOC117P
LOC117S
Mechanical Dimensions
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NTEGRATED
C
IRCUITS
D
IVISION
For additional information please visit our website at: www.ixysic.com
6
LOC117
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to
its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-LOC117-R05
©Copyright 2016, IXYS Integrated Circuits Division
OptoMOS® is a registered trademark of IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
2/1/2016
Dimensions
mm
(inches)
NOTES:
1. All dimensions carry tolerances of EIA Standard 481-2
2. The tape complies with all “Notes” for constant dimensions listed on page 5 of EIA-481-2
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
User Direction of Feed
P = 12.00
(0.472)
W = 16.00
(0.63)
Bo = 10.30
(0.406)
Ao = 10.30
(0.406)
K
1
= 2.00
(0.079)
K
0
= 2.70
(0.106)
7.50
(0.295)
2.00
(0.079)
4.00
(0.157)
Dimensions
mm
(inches)
User Direction of Feed
NOTES:
1. Dimensions carry tolerances of EIA Standard 481-2
2. Tape complies with all “Notes” for constant dimensions listed on page 5 of EIA-481-2
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
K
1
=4.20
(0.165)
0
K =4.90
(0.193)
P=12.00
(0.472)
W=16.00
(0.63)
Bo=10.30
(0.406)
Ao=10.30
(0.406)
LOC117PTR Tape & Reel
LOC117STR Tape & Reel

LOC117PTR

Mfr. #:
Manufacturer:
IXYS Integrated Circuits
Description:
High Linearity Optocouplers Single Linear Optocoupler
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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