MAX1970/MAX1971/MAX1972
troller can respond, the output deviates further,
depending on the inductor and output capacitor
values. After a short time (see the
Typical Operating
Characteristics
), the controller responds by regulating
the output voltage back to its nominal state. The con-
troller response time depends on the closed-loop
bandwidth. With a higher bandwidth, the response time
is faster, thus preventing the output from deviating fur-
ther from its regulating value.
Compensation Design
An internal transconductance error amplifier is used to
compensate the control loop. Connect a series resistor
and capacitor between COMP and GND to form a pole-
zero pair. The external inductor, internal high-side
MOSFET, output capacitor, compensation resistor, and
compensation capacitor determine the loop stability.
The inductor and output capacitor are chosen based
on performance, size, and cost. Additionally, the com-
pensation resistor and capacitor are selected to opti-
mize control-loop stability. The component values
shown in the typical application circuits (Figures 3, 4,
and 5) yield stable operation over a broad range of
input-to-output voltages.
The controller uses a current-mode control scheme that
regulates the output voltage by forcing the required
current through the external inductor. The voltage
across the internal high-side MOSFET’s on-resistance
(R
DS(ON)
) is used to sense the inductor current. Current
mode control eliminates the double pole caused by the
inductor and output capacitor, which has large phase
shift that requires more elaborate error-amplifier com-
pensation. A simple Type 1 compensation with single
compensation resistor (R
C
) and compensation capaci-
tor (C
C
) is all that is needed to have a stable and high-
bandwidth loop.
The basic regulator loop consists of a power modulator,
an output feedback divider, and an error amplifier. The
power modulator has DC gain set by gmc x R
LOAD
,
with a pole and zero pair set by R
LOAD
, the output
capacitor (C
OUT
), and its ESR. Below are equations
that define the power modulator:
The pole frequency for the modulator is:
The zero frequency for the output capacitor ESR is:
where, R
LOAD
= V
OUT
/I
OUT(MAX)
, and GMC = 2µS. The
feedback divider has a gain of G
FB
= V
FB
/V
OUT
, where
V
FB
is equal to 1.2V. The transconductance error ampli-
fier has a DC gain, G
EA(DC)
, of 60dB. A dominant pole
is set by the compensation capacitor, C
C
, the output
resistance of the error amplifier (R
OEA
), 20MΩ, and the
compensation resistor, R
C
. A zero is set by R
C
and C
C
.
The pole frequency set by the transconductance ampli-
fier output resistance, and compensation resistor and
capacitor is:
The zero frequency set by the compensation capacitor
and resistor is:
For best stability and response performance, the
closed-loop unity-gain frequency must be much higher
than the modulator pole frequency. In addition, the
closed-loop unity-gain frequency should be approxi-
mately 50kHz. The loop gain equation at unity gain fre-
quency then is:
Where G
EA(fc)
= gm
EA
R
C
, and G
MOD(fc)
= gmc
R
LOAD
fp
MOD
/
fc
, where gm
EA
= 50µS, R
C
can be
calculated as:
The error-amplifier compensation zero formed by R
C
and C
C
is set at the modulator pole frequency at maxi-
mum load. C
C
is calculated as follows:
