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XRA1203IL24TR-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
XRA1203
4
16-BIT I2C/SMBUS GPIO EXPANDER WITH RESET REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTIONS
1.1 I
2
C-bus Interface
The I
2
C-bus interface is compliant with the Standard-mode and Fast-mode I
2
C-bus specifications. The I
2
C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
The first byte sent by an I
2
C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA1203 responds to each write with an acknowledge
(SDA driven LOW by XRA1203 for one clock cycle when SCL is HIGH). The last byte sent by an I
2
C-bus
master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See
Figures 3 - 5 below.
For complete details, see the I
2
C-bus specifications.
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE
SWA A AP
SLAVE
ADDRESS
COMMAND
BYTE
DATA
BYTE
White block: host to XRA120x
Grey block: XRA120x to host
FIGURE 5. MASTER READS FROM SLAVE
SWA AR
SLAVE
ADDRESS
COMMAND
BYTE
White block: host to XRA120x
Grey block: XRA120x to host
AS
SLAVE
ADDRESS
nDATA ANAPLAST DATA
2
XRA1203
5
REV. 1.0.0 16-BIT I2C/SMBUS GPIO EXPANDER WITH RESET
1.1.1 I
2
C-bus Addressing
There could be many devices on the I
2
C-bus. To distinguish itself from the other devices on the I
2
C-bus, the
XRA1203 has up to 16 I
2
C slave addresses using the A1-A0 address lines. Table 1 below shows the different
addresses that can be selected.
TABLE 1: I C ADDRESS MAP
C ADDRESS
SCL GND 0x20 (0010 000X)
SCL VCC 0x22 (0010 001X)
SDA GND 0x24 (0010 010X)
SDA VCC 0x26 (0010 011X)
SCL SCL 0x30 (0011 000X)
SCL SDA 0x32 (0011 001X)
SDA SCL 0x34 (0011 010X)
SDA SDA 0x36 (0011 011X)
GND GND 0x40 (0100 000X)
GND VCC 0x42 (0100 001X)
VCC GND 0x44 (0100 010X)
VCC VCC 0x46 (0100 011X)
GND SCL 0x50 (0101 000X)
GND SDA 0x52 (0101 001X)
VCC SCL 0x54 (0101 010X)
VCC SDA 0x56 (0101 011X)
1.1.2 I
2
C Read and Write
A read or write transaction is determined by bit-0 of the slave address. If bit-0 is ’0’, then it is a write
transaction. If bit-0 is ’1’, then it is a read transaction.
2
A1 A0
I
2
XRA1203
6
16-BIT I2C/SMBUS GPIO EXPANDER WITH RESET REV. 1.0.0
1.1.3 I
2
C Command Byte
An I
2
C command byte is sent by the I
2
C master following the slave address. The command byte indicates the
address offset of the register that will be accessed.
Table 2 below lists the command bytes for each register.
TABLE 2: I C COMMAND BYTE (REGISTER ADDRESS)
COMMAND BYTE REGISTER NAME DESCRIPTION READ/WRITE DEFAULT VALUES
0x00 GSR1 - GPIO State for P0-P7 Read-Only 0xXX
0x01 GSR2 - GPIO State for P8-P15 Read-Only 0xXX
0x02 OCR1 - Output Control for P0-P7 Read/Write 0xFF
0x03 OCR2 - Output Control for P8-P15 Read/Write 0xFF
0x04 PIR1 - Input Polarity Inversion for P0-P7 Read/Write 0x00
0x05 PIR2 - Input Polarity Inversion for P8-P15 Read/Write 0x00
0x06 GCR1 - GPIO Configuration for P0-P7 Read/Write 0xFF
0x07 GCR2 - GPIO Configuration for P8-P15 Read/Write 0xFF
0x08 PUR1 - Input Internal Pull-up Resistor Enable/Disable for P0-P7 Read/Write 0x00
0x09 PUR2 - Input Internal Pull-up Resistor Enable/Disable for P8-P15 Read/Write 0x00
0x0A IER1 - Input Interrupt Enable for P0-P7 Read/Write 0x00
0x0B IER2 - Input Interrupt Enable for P8-P15 Read/Write 0x00
0x0C TSCR1 - Output Three-State Control for P0-P7 Read/Write 0x00
0x0D TSCR2 - Output Three-State Control for P8-P15 Read/Write 0x00
0x0E ISR1 - Input Interrupt Status for P0-P7 Read 0x00
0x0F ISR2 - Input Interrupt Status for P8-P15 Read 0x00
0x10 REIR1 - Input Rising Edge Interrupt Enable for P0-P7 Read/Write 0x00
0x11 REIR2 - Input Rising Edge Interrupt Enable for P8-P15 Read/Write 0x00
0x12 FEIR1 - Input Falling Edge Interrupt Enable for P0-P7 Read/Write 0x00
0x13 FEIR2 - Input Falling Edge Interrupt Enable for P8-P15 Read/Write 0x00
0x14 IFR1 - Input Filter Enable/Disable for P0-P7 Read/Write 0xFF
0x15 IFR2 - Input Filter Enable/Disable for P8-P15 Read/Write 0xFF
2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

XRA1203IL24TR-F

Mfr. #:
Buy XRA1203IL24TR-F
Manufacturer:
MaxLinear
Description:
Interface - I/O Expanders 16 Bit I2C GPIO Expander
Lifecycle:
New from this manufacturer.
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