FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
843001 DATA SHEET
10 REVISION B 11/16/15
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843001.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843001 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 93mA = 322.2mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 322.2mW + 30mW = 352.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.352W * 90.5°C/W = 116.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ
JA
FOR 8-PIN TSSOP, FORCED CONVECTION
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
REVISION B 11/16/15
843001 DATA SHEET
11 FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC
_MAX
- V
OH_MAX
))
/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC
_MAX
- V
OL_MAX
))
/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 4. LVPECL DRIVER CIRCUIT AND T ERMINATION
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
843001 DATA SHEET
12 REVISION B 11/16/15
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 843001 is: 1702
TABLE 8. θ
JA
VS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

843001AG-123LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 1 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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