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licensed by Power.org. © 2011 Freescale Semiconductor, Inc.
Document Number: QP3041FS REV 3
To learn more about Freescale QorIQ communications
platforms, please visit freescale.com/QorIQ
Key Architectural Features
• Three-levelcachehierarchy:Thelow-
latency32KBL1instructionanddata
caches are augmented by a unified 128
KBprivatebacksideL2cachepercore.
TheL2is8-waysetassociativeandisECC
protected. When instructions are locked in
theL2,theper-packet“hot”codeisalways
readily available, improving application
performance. A shared 1 MB CoreNet
platformcache(L3)facilitatescore-to-core
communications and minimizes accesses to
main memory.
• Hardwarehypervisor:Thee500mcsupports
a hardware hypervisor that is designed to
enable each core to run its own operating
system completely independent of the other
core. The hypervisor facilitates resource
sharing and partitioning in a multicore
environment, and provides protection in
the event that a core, driven by malicious
or improperly programmed code, tries to
access memory it does not have permission
to read or write. It also allows the sharing and
partitioning of various I/Os across the cores
and it helps ensure that incoming memory
mapped transactions are written only into
appropriate ranges of the memory map.
• DPAA:Thisoffloadsthecoresfromthe
need to perform routine packet-handling
tasks. For instance, the DPAA will extract
headers from incoming packets, police
them, classify them and manage their data
buffers. The work is assigned to cores
with a three-level scheduling hierarchy,
which can also facilitate sharing of packet
workload over multiple cores.
• CoreNetswitchfabric:Thefabric-based
interface provides scalable on-chip, point-
to-point connectivity supporting concurrent
traffic to and from multiple resources
connected to the fabric, eliminating single-
point bottlenecks for non-competing
resources. This is designed to eliminate bus
contention and latency issues associated
with scaling shared bus architectures that
are common in other multicore approaches.
Target Applications
The P3 family is targeted at mixed control
plane and data plane applications, where in
previous generations separate devices would
implement each function. Typically, one or
two cores would implement the control plane,
while the remaining cores implement the data
plane. The hardware hypervisor facilitates this,
with its capability to safely provision flexible
core allocations into groups running SMP, one
core running alone, separate cores running in
parallel or a core running end-user applications.
There are many applications that look similar to
this, including:
• Integratedaccessrouter(IAD):DualSATA
ports provide high-speed, cost-effective
storage options for statistics or large
databases. Compared to SGMII, 2.5
GbpsEthernetenablesthenextstepin
performance connectivity to switches.
• Basestationnetworkinterfacecard(NIC):
Dual Serial RapidIO
®
ports(upto5GHz)
can be used for redundancy or multiple
connections, both to the backplane or
to the DSP farm. With improved Type 11
messaging and new support for Type 9 data
streaming, the Serial RapidIO interconnect
can now be used not only as a control plane
interface, but can also achieve its intended
potential as a highly efficient data path.
Features
Four e500mc cores, built on
Power Architecture technology
• Upto1.5GHz
• Eachwith128KBbacksideL2cache
Memory controller
• DDR3,3Lupto1.3GHz
• 32/64-bitdatabuswithECC
High-speed interconnects
• 18x5GHzSerDeslanes
• 4xPCIExpress
®
2.0 controllers at up to
5GHz
• 2xSerialRapidIO1.3/2.1controllersatup
to5GHz
• 2xSATA2.0at3Gbps
• 2xUSB2.0withPHY
CoreNet switch fabric
• 1MBsharedCoreNetplatformcache(L3)
withECC
Ethernet
• 5x10/100/1000Ethernetcontroller
• 1x10GigabitEthernetcontrollers
• Allwithclassification,hardwarequeueing,
policing, buffer management, checksum
offload, QoS, lossless flow control,
IEEE
®
1588
• Upto1xXAUI,4xSGMIIor2.5Gbps
SGMII, 2x RGMII
Data path acceleration
• SEC4.2:publickeyaccelerator,DES,
AES,messagedigestaccelerator,random
number generator, ARC4, SNOW 3G F8
and F9, CRC, Kasumi
• PME2.1:searchesfor128bytetextstrings
in 32 KB patterns in 128M sessions
• RapidIOmessaging:Type9and11
Device
• 45nmSOIprocesstechnology
• 1295-pinFCPBGApackage,37.5mmx
37.5 mm
Enablement
• Enea
®
: Real-time operating system support
• GreenHills
®
: Complete portfolio of software
and hardware development tools, trace
tools and real-time operating systems
• MentorGraphics
®
: Commercial grade
Linux
®
solution
• CodeSourcery:Toolchainsupportfornew
core technology
• WindRiver
®
: Simics
®
model
• Developmentsystem:FourPCIExpress
slots,oneSerialRapidIOslot,oneXAUI
slot, one SGMII slot, SATA disk, Aurora
debug port