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R5F21122DFP#U0

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
R8C/12 Group 2. Central Processing Unit (CPU)
Rev.1.20 Jan 27, 2006 page 8 of 25
REJ03B0068-0120
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing.
They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can
be combined with A0 to be used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch
between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag
is set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
R8C/12 Group 3. Memory
Rev.1.20 Jan 27, 2006 page 9 of 25
REJ03B0068-0120
3. Memory
Figure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses
0000016 to FFFFF16.
The internal ROM (program ROM) is allocated lower addresses beginning with address 0FFFF16. For
example, a 16-Kbyte internal ROM is allocated addresses from 0C00016 to 0FFFF16.
The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting
address of each interrupt routine.
The internal ROM (data flash) is allocated addresses from 0200016 to 02FFF16.
The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte
internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing
data, but for calling subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function
control registers are located them. All addresses, which have nothing allocated within the SFR, are re-
served area and cannot be accessed by users.
Figure 3.1 Memory Map
0
0
0
0
0
1
6
0
Y
Y
Y
Y
1
6
0
F
F
F
F
1
6
0
0
2
F
F
1
6
00400
16
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0FFDC
16
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Overflow
BRK instruction
Address match
Single step
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Type name
0
X
X
X
X
1
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Internal RAM
F
F
F
F
F
1
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A
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6
005FF
16
Internal RAM
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007FF
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5
1
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1
K
b
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006FF
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7
6
8
b
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Address 0YYYY
16
0E000
16
Internal ROM
S
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e
0C000
16
8K bytes
16K bytes
0D000
16
12K bytes
Expansion area
(Reserved)
R
5
F
2
1
1
2
4
F
P
,
R
5
F
2
1
1
2
4
D
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5
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1
1
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3
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5
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2
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1
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3
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1
1
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2
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2
D
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0
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F
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R8C/12 Group 4. Special Function Register (SFR)
Rev.1.20 Jan 27, 2006 page 10 of 25
REJ03B0068-0120
Watchdog timer start register WDTS XX
16
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RX
X
X
X
X
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0
0
2
Protect register PRCR 00XXX000
2
Processor mode register 1 PM1 00XXX0X0
2
N
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S
:
1
.
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0
FX
X
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0
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2
0
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1
6
0
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1
1
6
0
0
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2
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6
0
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3
1
6
0
0
0
4
1
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0
0
0
5
1
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0
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0
6
1
6
0
0
0
7
1
6
0
0
0
8
1
6
0
0
0
9
1
6
0
0
0
A
1
6
0
0
0
B
1
6
0
0
0
C
1
6
0
0
0
D
1
6
0
0
0
E
1
6
0
0
0
F
1
6
0
0
1
0
1
6
0
0
1
1
1
6
0
0
1
2
1
6
0
0
1
3
1
6
0
0
1
4
1
6
0
0
1
5
1
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0
0
1
6
1
6
0
0
1
7
1
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0
0
1
8
1
6
0
0
1
9
1
6
0
0
1
A
1
6
0
0
1
B
1
6
0
0
1
C
1
6
0
0
1
D
1
6
0
0
1
E
1
6
0
0
1
F
1
6
0
0
2
0
1
6
0
0
2
1
1
6
0
0
2
2
1
6
0
0
2
3
1
6
0
0
2
4
1
6
0
0
2
5
1
6
0
0
2
6
1
6
0
0
2
7
1
6
0
0
2
8
1
6
0
0
2
9
1
6
0
0
2
A
1
6
0
0
2
B
1
6
0
0
2
C
1
6
0
0
2
D
1
6
0
0
2
E
1
6
0
0
2
F
1
6
0
0
3
0
1
6
0
0
3
1
1
6
0
0
3
2
1
6
0
0
3
3
1
6
0
0
3
4
1
6
0
0
3
5
1
6
0
0
3
6
1
6
0
0
3
7
1
6
0
0
3
8
1
6
0
0
3
9
1
6
0
0
3
A
1
6
0
0
3
B
1
6
0
0
3
C
1
6
0
0
3
D
1
6
0
0
3
E
1
6
0
0
3
F
1
6
A
d
d
r
e
s
s
Register Symbol After reset
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
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g
i
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t
e
r
0R
M
A
D
00
0
1
6
0
0
1
6
X
0
1
6
A
d
d
r
e
s
s
m
a
t
c
h
i
n
t
e
r
r
u
p
t
r
e
g
i
s
t
e
r
1R
M
A
D
10
0
1
6
0
0
1
6
X
0
1
6
W
a
t
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h
d
o
g
t
i
m
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r
r
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s
e
t
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g
i
s
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e
rW
D
T
RX
X
1
6
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR
information
Table 4.1 SFR Information(1)
(1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

R5F21122DFP#U0

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Buy R5F21122DFP#U0
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU MCU 3/5V 8K I-Temp Pb-Free 32-LQFP
Lifecycle:
New from this manufacturer.
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