ADCMP380 Data Sheet
Rev. A | Page 8 of 10
THEORY OF OPERATION
The ADCMP380 ultralow power voltage comparator is especially
suited for battery-powered applications due to the maximum
190 nA quiescent current. The internal precision reference
and the low input leakage current allow the user to monitor the
voltage of interest accurately through external resistor dividers.
The device features internal input hysteresis and an open-drain
output. The output remains logic high after the voltage on the
IN pin is above the internal reference voltage. The device keeps
the output in a logic low state whenever the supply voltage on
the VCC pin is below the UVLO threshold. The output can be
disabled and remains low if the EN pin is pulled low, regardless of
the status of the IN pin.
TRANSIENT IMMUNITY
To avoid unnecessary output state change caused by fast power
supply transients, an input glitch filter is added to the IN pin of
the ADCMP380 to filter out the transient glitches on the pin.
Figure 8 shows the comparator overdrive (that is, the maximum
magnitude of positive and negative going pulses with respect to
the reference voltage) vs. the pulse duration without changing
the state of the output.
OUTPUT
The output of ADCMP380 comparator is open-drain. The
output is guaranteed to be logic low from when V
CC
= 0.9 V to
when the device exits ULVO.
When the IN voltage falls below the internal reference voltage,
the OUT pin asserts low within 23 μs (typical). When the
monitored voltage rises above the reference voltage plus
hysteresis, the OUT pin asserts high within 39.5 μs.
EN INPUT
Driving EN low asserts the output low. The EN input has a
0.6 MΩ internal pull-up resistor so that the input is always high
when unconnected. To drive the EN input, use an external signal
or a push-button switch to ground; debounce circuitry is integrated
on-chip for this purpose. Noise immunity is provided on the EN
input, and fast, negative going transients of up to 0.4 μs (typical) are
ignored. If required, a 0.1 μF capacitor between the EN pin and
ground provides additional noise immunity.
Figure 14. Timing Diagram
ADDING HYSTERESIS
To prevent oscillations at the output caused by noise or slowly
moving signals passing the switching threshold, positive feedback
can add hysteresis to the input.
For the configuration shown in Figure 15, connect the bottom
end of the input resistor divider to the output; the effective
threshold is altered based on the output state.
The input falling threshold level is given by
( )
PULLUP
SUPPLY
PULLUPREF
FALLIN
RR2
R1VRR2R1V
V
+
++
=
–
_
where V
REF
= 0.6 V, assuming R
LOAD
>> R2 and R
PULLUP,
where
R
LOAD
is the resistance on the load.
The input rising threshold level is given by
( )
R2
R2R1V
V
REF
RISE
IN
+
=
_
The additional hysteresis is the difference between these voltage
levels and is given by
PULLUP
SUPPLYPULLUPREF
IN
RR2R2R2
R1R2VR1RV
V
×+×
+
=∆
Note that the built in hysteresis of the device is neglected in this
calculation.
Figure 15. Configuration with Added Hysteresis
VCC
OUT
EN
UVLO
R
EN EXTERNALLY
DRIVEN LOW
IN
V
REF
+ V
HYST
t
PD
t
PD
t
D_EN
t
D_EN
V
REF
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IN
R1
R2
V
IN
V
SUPPLY
VCC
EN
GND
R
LOAD
R
PULLUP
OUT
REF
ADCMP380
12783-015
