LTC1663
5
1663fd
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation vs Output Current
Offset Error Voltage vs
Temperature
Full-Scale Output Voltage vs
Temperature
I
OUT
(mA)
–1.0
–1.0
ΔV
OUT
(LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
–0.6 –0.4
0
0.2
1663 G07
–0.6
0.6
0.8
0.2
–0.8 –0.2
0.60.4
0.8
1.0
V
CC
= V
REF
= 3V
V
OUT
= 1.5V
CODE = 512
T
A
= 25°C
SOURCE SINK
TEMPERATURE (°C)
–60
OFFSET ERROR VOLTAGE (mV)
5
4
3
2
1
0
–1
–2
–3
–4
–5
–20
20
40
1663 G08
–40 0
60
80
100
TEMPERATURE (°C)
–60
OUTPUT VOLTAGE (V)
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
–20
20
40
1663 G09
–40 0
60
80
100
REFERENCE SET TO
INTERNAL BANDGAP
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged
by the SDA pin. High impedance pin while data is shifted
in. Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to V
CC
.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1663’s slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1663’s slave address.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin.
Data is shifted into the SDA pin at the rising edges of the
clock. This high impedance pin requires a pull-up resistor
or current source to V
CC
.
V
CC
(Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ V
CC
≤ 5.5V. Also used as the reference voltage input when the
part is programmed to use V
CC
as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1663’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
V
OUT
(Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
rail-to-rail DAC output.
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (ΔV
OUT
– LSB)/LSB
Where ΔV
OUT
is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the ana-
log output caused by AC coupling from the digital inputs
when they change state. The area of the glitch is specifi ed
in (nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
DEFINITIONS
PIN FUNCTIONS
