AD779JNZ Datasheet AD779KD, AD779JNZ, AD779JDZ | P10-P12

AD779

–9–

REV. B

BIPOLAR RANGE INPUTS

The connections for the bipolar mode are shown in Figure 5. In

this mode, data output coding will be twos complement binary.

This circuit will allow approximately ±25 mV of offset trim

range (±40 LSB) and ±0.5% of gain trim range (±80 LSB).

Figure 5. Bipolar Input Connections with Gain and

Offset Trims

Either or both of the trim pots can be replaced with 50 Ω ±1%

fixed resistors if the AD779 accuracy limits are sufficient for the

application. If the pins are shorted together, the additional offset

and gain errors will be approximately 80 LSB.

To trim bipolar zero to its nominal value, apply a signal 1/2 LSB

below midrange (–0.305 mV for a ±5 V range) and adjust R1

until the major carry transition is located (11 1111 1111 1111 to

00 0000 0000 0000). To trim the gain, apply a signal 1 1/2 LSB

below full scale (+4.9991 V for a ±5 V range) and adjust R2 to

give the last positive transition (01 1111 1111 1110 to 01 1111

1111 1111). These trims are interactive so several iterations may

be necessary for convergence.

A single pass calibration can be done by substituting a bipolar

offset trim (error at minus full scale) for the bipolar zero trim

(error at midscale), using the same circuit. First, apply a signal

1/2 LSB above minus full scale (–4.9997 V for a ±5 V range)

and adjust R1 until the minus full-scale transition is located

(10 0000 0000 0000 to 10 000 000 0001). Then perform the

gain error trim as outlined above.

UNIPOLAR RANGE INPUTS

Offset and gain errors can be trimmed out by using the configu-

ration shown in Figure 6. This circuit allows approximately

±25 mV of offset trim range (±40 LSB) and ±0.5% of gain trim

range (±80 LSB).

Figure 6. Unipolar Input Connections with Gain and

Offset Trims

The first transition (from 00 0000 0000 0000 to 00 0000 0000

0001) should nominally occur for an input level of +1/2 LSB

(0.305 mV above ground for a 10 V range). To trim unipolar

zero to this nominal value, apply a 0.305 mV signal to AIN and

adjust R1 until the first transition is located.

The gain trim is done by adjusting R2. If the nominal value is

required, apply a signal 1 1/2 LSB below full scale (9.9997 V for

a 10 V range) and adjust R2 until the last transition is located

(11 1111 1111 1110 to 11 1111 1111 1111).

If offset adjustment is not required, BIPOFF should be con-

nected directly to AGND. If gain adjustment is not required, R2

should be replaced with a fixed 50 Ω ±1% metal film resistor. If

REF

OUT

is connected directly to REF

, the additional gain

error will be approximately 1%.

REFERENCE DECOUPLING

It is recommended that a 10 µF tantalum capacitor be

connected between REF

(Pin 9) and ground. This has the

effect of improving the S/N+D ratio through filtering possible

broadband noise contributions from the voltage reference.

BOARD LAYOUT

Designing with high resolution data converters requires careful

attention to board layout. Trace impedance is a significant issue.

A 1.22 mA current through a 0.5 Ω trace will develop a voltage

drop of 0.6 mV, which is 1 LSB at the 14-bit level for a 10 V

full-scale span. In addition to ground drops, inductive and

capacitive coupling need to be considered, especially when high

accuracy analog signals share the same board with digital signals.

Finally, power supplies need to be decoupled in order to filter

out ac noise.

Analog and digital signals should not share a common path.

Each signal should have an appropriate analog or digital return

routed close to it. Using this approach, signal loops enclose a

small area, minimizing the inductive coupling of noise. Wide PC

tracks, large gauge wire, and ground planes are highly recom-

mended to provide low impedance signal paths. Separate analog

and digital ground planes are also desirable, with a single

interconnection point to minimize ground loops. Analog signals

should be routed as far as possible from digital signals and

should cross them at right angles.

The AD779 incorporates several features to help the user’s layout.

Analog pins (V

) AIN, AGND, REF

OUT

, REF

, BIPOFF,

) are adjacent to help isolate analog from digital signals. In

addition, the 10 MΩ input impedance of AIN minimizes input

trace impedance errors. Finally, ground currents have been

minimized by careful circuit design. Current through AGND is

200 µA, with no code dependent variation. The current through

DGND is dominated by the return current for DB13–DB0 and

EOC.

SUPPLY DECOUPLING

The AD779 power supplies should be well filtered, well regulated,

and free from high frequency noise. Switching power supplies

are not recommended due to their tendency to generate spikes

which can induce noise in the analog system.

Decoupling capacitors should be used as close as possible to all

power supply pins. A 10 µF tantalum capacitor in parallel with a

0.1 µF ceramic capacitor provides adequate decoupling.

AD779

–10–

REV. B

An effort should be made to minimize the trace length between

the capacitor leads and the respective converter power supply

and common pins. The circuit layout should attempt to locate

the AD779, associated analog input circuitry and interconnec-

tions as far as possible from logic circuitry. A solid analog

ground plane around the AD779 will isolate large switching

ground currents. For these reasons, the use of wire wrap circuit

construction is not recommended; careful printed circuit con-

struction is preferred.

GROUNDING

If a single AD779 is used with separate analog and digital

ground planes, connect the analog ground plane to AGND and

the digital ground plane to DGND keeping lead lengths as short

as possible. Then connect AGND and DGND together at the

AD779. If multiple AD779s are used or the AD779 shares

analog supplies with other components, connect the analog and

digital returns together once at the power supplies rather than at

each chip. This prevents large ground loops which inductively

couple noise and allow digital currents to flow through the

analog system.

USE OF EXTERNAL VOLTAGE REFERENCE

The AD779 features an on-chip voltage reference. For improved

gain accuracy over temperature, a high performance external

voltage reference may be used in place of the on-chip reference.

The AD586 and AD588 are popular references appropriate for

use with high resolution converters. The AD586 is a low cost

reference which utilizes a buried Zener architecture to provide

low noise and drift. The AD588 is a higher performance refer-

ence which uses a proprietary ion-implanted buried Zener diode

in conjunction with laser-trimmed thin-film resistors for low off-

set and low drift.

Figure 7 shows the use of the AD586 with the AD779 in a bipo-

lar input mode. Over the 0°C to +70°C range, the AD586 L-grade

exhibits less than a 2.25 mV output change from its initial value

at 25°C. REF

, (Pin 9) scales its input by a factor of two; thus,

this change becomes effectively 4.5 mV. When applied to the

AD779, this results in a total gain drift of 0.09% FSR which is

an improvement over the on-chip reference performance of

0.11% FSR. A noise-reduction capacitor, C

, has been shown.

This capacitor reduces the broadband noise of the AD586 out-

put, thereby optimizing the overall ac and dc performance of the

AD779.

Figure 7. Bipolar Input with Gain and Offset Trims

Figure 8 shows the AD779 in unipolar input mode with the

AD588 reference. The AD588 output is accurate to 0.65 mV

from its value at 25°C over the 0°C to 70°C range. This results

in a 0.06% FSR total gain drift for the AD779, which is a sub-

stantial improvement over the on-chip reference performance of

0.11% FSR. A noise-reduction network on Pins 4, 6 and 7 has

been shown. The 1 µF capacitors form low pass filters with the

internal resistance of the AD588 Zener and amplifier cells and

external resistance. This reduces the high frequency noise of

the AD588, providing optimum ac and dc performance of the

AD779.

Figure 8. Unipolar Input with Gain and Offset Trims

INTERFACING THE AD779 TO MICROPROCESSORS

The I/O capabilities of the AD779 allow direct interfacing to

general purpose and DSP microprocessor buses. The asynchro-

nous conversion control feature allows complete flexibility and

control with minimal external hardware.

The following examples illustrate typical AD779 interface

configurations.

AD779 TO TMS320C25

In Figure 9 the AD779 is mapped into the TMS320C25 I/O

space. AD779 conversions are initiated by issuing an OUT

instruction to Port 1. EOC status and the conversion result are

read in with an IN instruction to Port 1. A single wait state is

inserted by generating the processor READY input from

IS,

Port 1 and

MSC. This configuration supports processor clock

speeds of 20 MHz and is capable of supporting processor clock

speeds of 40 MHz if a NOP instruction follows each AD779

read instruction.

Figure 9. AD779 to TMS320C25 Interface

AD779

–11–

REV. B

AD779 TO 80186

Figure 10 shows the AD779 interfaced to the 80186 micropro-

cessor. This interface allows the 80186’s built-in DMA control-

ler to transfer the AD779 output into a RAM based FIFO buffer

of any length, with no microprocessor intervention.

Figure 10. AD779 to 80186 DMA Interface

AD779 TO Z80

The AD779 can be interfaced to the Z80 processor in an I/O or

memory mapped configuration. Figure 11 illustrates an I/O con-

figuration, where the AD779 occupies several port addresses to

allow separate polling of the EOC status and reading of the data.

Figure 11. AD779 to Z80 Interface

A useful feature of the Z80 is that a single wait state is automati-

cally inserted during I/O operations, allowing the AD779 to be

used with Z80 processors having clock speeds up to 8 MHz.

The AD779 is asynchronous which allows conversions to be ini-

tiated by an external trigger source independent of the micro-

processor clock. After each conversion, the AD779 EOC signal

generates a DMA request to Channel 1 (DRQ1). The subse-

quent DMA READ resets the interrupt latch. The system de-

signer must assign a sufficient priority to the DMA channel to

ensure that the DMA request will be serviced before the com-

pletion of the next conversion. This configuration can be used

with 6 MHz and 8 MHz 80186 processors.

AD779 TO ANALOG DEVICES ADSP-2100A

Figure 12 demonstrates the AD779 interfaced to an ADSP-

2100A. With a clock frequency of 12.5 MHz, and instruction

execution in one 80 ns cycle, the digital signal processor will

support the AD779 data memory interface with two wait states.

The converter runs asychronously using a sampling clock. The

EOC output to the AD779 gets asserted at the end of each

conversion and causes an interrupt. Upon interrupt, the ADSP-

2100A starts a data memory read by providing an address on

the DMA bus. The decoded address generates

OE for the

converter.

OE, together with logic and latch, is used to force the

ADSP-2100A into a one cycle wait state by generating

DMACK. The read operation is thus started and completed

within two processor cycles (160 ns).

Figure 12. AD779 to ADSP-2100A Interface

Figure 13. Harmonic Distortion vs. Input Frequency

(0.5 dB Input)

Figure 14. Total Harmonic Distortion vs. Input Frequency

and Amplitude

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD779JNZ

Mfr. #:

Buy AD779JNZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 14-Bit 128kSPS Complete Sampling

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AD779JNZ

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