AD779
–6–
REV. B
PIN DESCRIPTION
28-Pin DIP
Symbol Pin No. Type Name and Function
AGND 7 P Analog Ground. This is the ground return for AIN only.
AIN 6 AI Analog Signal Input.
BIPOFF 10 AI Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight
binary output coding. Connect to REF
OUT
for ±5 V input
bipolar mode and twos-complement binary output coding.
CS 12 DI Chip Select. Active LOW.
DGND 14 P Digital Ground.
DB13–DB0 28–15 DO Data Bits. These pins provide all 14 bits in one 14 bit parallel output.
Active HIGH.
EOC 2 DO End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH
when the conversion is finished. EOC is a three-state output. See
EOCEN pin for information on EOC gating.
EOCEN 13 DI End-of-Convert Enable. Enables EOC pin. Active LOW.
OE 3 DI Output Enable. A down-going transition on OE enables data bits.
Active LOW.
REF
IN
9 AI Reference Input. +5 V input gives 10 V full scale range.
REF
OUT
8 AO +5 V Reference Output. Tied to REF
IN
for normal operation.
SC 4 DI Start Convert. Active LOW.
V
CC
11 P +12 V Analog Power.
V
EE
5 P –12 V Analog Power.
V
DD
1 P +5 V Digital Power.
Type: AI = Analog Input.
AO = Analog Output.
DI = Digital Input.
DO = Digital Output. All DO pins are three-state drivers.
P = Power.
PIN CONFIGURATION
DIP Package
AD779
–7–
REV. B
DEFINITION OF SPECIFICATIONS
NYQUIST FREQUENCY
An implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of a full-scale input signal and is
expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
INTERMODULATION DISTORTION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are
those for which m or n is not equal to zero. For example, the
second order terms are (fa + fb) and (fa – fb) and the third order
terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The
IMD products are expressed as the decibel ratio of the rms sum
of the measured input signals to the rms sum of the distortion
terms. The two signals applied to the converter are of equal
amplitude and the peak value of their sum is –0.5 dB from full
scale (9.44 V p-p). The IMD products are normalized to a 0-dB
input signal.
BANDWIDTH
The full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than –0.1 dB. Beyond this frequency,
distortion of the sampled input signal increases significantly.
The AD779 has been designed to optimize input bandwidth,
allowing it to undersample input signals with frequencies
significantly above the converter’s Nyquist frequency.
APERTURE DELAY
Aperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Start Convert (
SC) to when
the input signal is held for conversion.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
INPUT SETTLING TIME
Settling time is a function of the SHA’s ability to track fast
slewing signals. This is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
DIFFERENTIAL NONLINEARITY (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
linearity is the deviation from this ideal value. It is often
specified in terms of resolution for which no missing codes
(NMC) are guaranteed.
INTEGRAL NONLINEARITY (INL)
The ideal transfer function for a linear ADC is a straight line
drawn between “zero” and “full scale.” The point used as
“zero” occurs 1/2 LSB before the first code transition. “Full
scale” is defined as a level 1 1/2 LSB beyond the last code
transition. Integral nonlinearity error is the worst case deviation
of a code from the straight line. The deviation of each code is
measured from the middle of that code.
Note that the linearity error is not user adjustable.
POWER SUPPLY REJECTION
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
TEMPERATURE DRIFT
This is the maximum change in the parameter from the initial
value (@+25°C) to the value at T
MIN
or T
MAX
.
UNIPOLAR ZERO ERROR
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the
deviation of the actual transition from that point. This error
can be adjusted as discussed in the Input Connections and
Calibration section.
BIPOLAR ZERO ERROR
In the bipolar mode, the major carry transition (11 1111 1111
1111 to 00 0000 0000 0000 ) should occur at an analog value
1/2 LSB below analog ground. Bipolar zero error is the deviation
of the actual transition from that point. This error can be
adjusted as discussed in the Input Connections and Calibration
section.
GAIN ERROR
The last transition should occur at an analog value 1 1/2 LSB
below the nominal full scale (9.9991 volts for a 0 V–10 V range,
4.9991 volts for a ±5 V range). The gain error is the deviation of
the actual level at the last transition from the ideal level with the
zero error trimmed out. This error can be adjusted as shown in
the Input Connections and Calibration section.
AD779
–8–
REV. B
CONVERSION CONTROL
Before a conversion is started, End-of-Convert (EOC) is HIGH
and the sample-hold is in track mode. A conversion is started by
bringing
SC LOW, regardless of the state of CS.
After a conversion is started, the sample-hold goes into hold
mode and EOC goes LOW, signifying that a conversion is in
progress. During the conversion, the sample-hold will go back
into track mode and start acquiring the next sample.
In track mode, the sample-hold will settle to ±0.003% (14 bits)
in 1.5 µs maximum. The acquisition time does not affect the
throughput rate as the AD779 goes back into track mode more
than 2 µs before the next conversion. In multichannel systems,
the input channel can be switched as soon as EOC goes LOW if
the maximum throughput rate is needed.
When EOC goes HIGH, the conversion is completed and the
output data may be read. Bringing
OE LOW makes the output
register contents available on the output data bits (DB13–DB0).
A period of time t
CD
is required after OE is brought HIGH
before the next
SC instruction is issued.
If
SC is held LOW, conversion accuracy may deteriorate. For
this reason,
SC should not be held low in any attempt to operate
in a continuously converting mode.
END-OF-CONVERT
End-of-Convert (EOC) is a three-state output which is enabled
by End-of-Convert Enable
EOCEN.
OUTPUT ENABLE OPERATION
The data bits (DB13–DB0) are three-state outputs that are
enabled by Chip Select (
CS) and Output Enable (OE). CS
should be LOW t
OE
before OE is brought LOW. The output is
read in a single cycle as a 14-bit word.
In unipolar mode (BIPOFF tied to AGND), the output coding
is straight binary. In bipolar mode (BIPOFF tied to REF
OUT
),
output coding is twos complement binary.
POWER-UP
The AD779 typically requires 10 µs after power-up to reset
internal logic
14-BIT MODE CODING FORMAT (1 LSB = 0.61 mV)
Unipolar Coding Bipolar Coding
(Straight Binary) (Twos Complement)
V
IN
Output Code V
IN
Output Code
0.00000 V 000 . . . 0 –5.00000 V 100 . . . 0
5.00000 V 100 . . . 0 –0.00061 V 111 . . . 1
9.99939 V 111 . . . 1 0.00000 V 000 . . . 0
+2.50000 V 010 . . . 0
+4.99939 V 011 . . . 1
Application Information
INPUT CONNECTIONS AND CALIBRATION
The high (10 M) input impedance of the AD779 eases the
task of interfacing to high source impedances or multiplexer
channel-to-channel mismatches of up to 300 . The 10 V p-p
full-scale input range accepts the majority of signal voltages
without the need for voltage divider networks which could
deteriorate the accuracy of the ADC.
The AD779 is factory trimmed to minimize offset, gain and
linearity errors. In unipolar mode, the only external component
that is required is a 50 ± 1% resistor. Two resistors are
required in bipolar mode. If offset and gain are not critical, even
these components can be eliminated.
In some applications, offset and gain errors need to be more
precisely trimmed. The following sections describe the correct
procedure for these various situations.
CONVERSION TRUTH TABLE
INPUTS OUTPUTS
Mode SC EOCEN CS OE EOC DB13 . . . DB0 Status
Start Conversion 1 X X X No Conversion
f X X X Start Conversion
0 X X X Continuous Conversion (Not Recommended)
Conversion Status X 0 X X 0 Converting
X 0 X X 1 Not Converting
X 1 X X High Z Either
Data Access X X X 1 High Z Three-State
X X 1 X High Z Three-State
X X 0 0 MSB . . . LSB Data Out
NOTES
1 = HIGH voltage level.
0 = LOW voltage level.
X = Don’t care.
f = HIGH to LOW transition. Must stay LOW for t = t
CP
.

AD779KD

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14-Bit 128kSPS Complete Sampling
Lifecycle:
New from this manufacturer.
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