DS1640/DS1640C
2 of 4
OPERATION
With +3 Û +5 volts applied between the V
CC
pin and ground, any one of four inputs can be connected or
disconnected from its respective output based on the bias applied to the control gate (see Figure 1). A set
of four internal latches is controlled by the latch input. The logic levels passed to the FET gates are
controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are
inverted and passed directly to the control gates, enabling the switches to be switched both independently
and asynchronously. With a transition from logic 0 to logic 1 on the latch pin, the input levels present on
the gate inputs are locked by the four internal latches, maintaining the corresponding FET gates at those
levels. As long as the latch input is maintained at logic 1, the FET gate levels are maintained. When the
latch input is returned to logic 0, the gate inputs again are inverted and passed to the FET control gates
without being latched. A TTL or CMOS logic 1 turns a switch completely on and TTL or CMOS logic 0
turns a switch completely off. The four switches can be operated independently or two or more can be
connected in parallel for added current carrying capability. The four switches contained within the
DS1640 are not designed to be operated in a linear manner. When V
CC
is not applied to the DS1640 or if
V
CC
is not within nominal limits, the output levels and current carrying capability of the four switches are
not guaranteed. When all four gate inputs are off (logic 0) the device enters a low V
CC
current standby
mode because the onboard charge pump is turned off. The gate and latch inputs are CMOS-compatible
throughout the entire V
CC
range and are TTL-compatible when V
CC
falls between 4.5 and 5.5V.
DS1640 BLOCK DIAGRAM Figure 1
