September 1993 2
Philips Semiconductors Product specification
Quad bilateral switches 74HC/HCT4316
FEATURES
• Low “ON” resistance:
160 Ω (typ.) at V
CC
− V
EE
= 4.5 V
120 Ω (typ.) at V
CC
− V
EE
= 6.0 V
80 Ω (typ.) at V
CC
− V
EE
= 9.0 V
• Logic level translation:
to enable 5 V logic to communicate
with ± 5 V analog signals
• Typical “break before make” built in
• Output capability: non-standard
• I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4316 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4316 have four independent analog
switches. Each switch has two input/output terminals
(nY, nZ) and an active HIGH select input (nS). When the
enable input (
E) is HIGH, all four analog switches are
turned off.
Current through a switch will not cause additional V
CC
current provided the voltage at the terminals of the switch
is maintained within the supply voltage range;
V
CC
>> (V
Y
, V
Z
) >> V
EE
. Inputs nY and nZ are electrically
equivalent terminals.
V
CC
and GND are the supply voltage pins for the digital
control inputs (E and nS). The V
CC
to GND ranges are 2.0
to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY and nZ) can swing between
V
CC
as a positive limit and V
EE
as a negative limit.
V
CC
− V
EE
may not exceed 10.0 V.
See the “4016” for the version without logic level
translation.
QUICK REFERENCE DATA
V
EE
= GND = 0 V; T
amb
=25°C; t
r
=t
f
= 6 ns
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PZH
turn “ON” time C
L
= 15 pF; R
L
=1 kΩ;
V
CC
=5 V
E to V
OS
19 19 ns
nS to V
OS
16 17 ns
t
PZL
turn “ON” time
E to V
OS
19 24 ns
nS to V
OS
16 21 ns
t
PHZ
/ t
PLZ
turn “OFF” time
E to V
OS
20 21 ns
nS to V
OS
16 19 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per switch notes 1 and 2 13 14 pF
C
S
max. switch capacitance 5 5 pF
Notes
1. C
PD
is used to determine the dynamic power
dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+∑{(C
L
+C
S
)×V
CC
2
× f
o
}
where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑ {(C
L
+C
S
)×V
CC
2
× f
o
} = sum of outputs
C
L
= output load capacitance in pF
C
S
= max. switch capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
− 1.5 V
